公开(公告)号：US20250013256A1

公开(公告)日：2025-01-09

申请号：US18361932

申请日：2023-07-31

Applicant: Kang-Shuo Chang ,  KAORU TAKASUKA

Inventor： Kang-Shuo Chang ,  KAORU TAKASUKA

IPC: G05F3/16

Abstract: A reference current generating circuit including a reference voltage generating circuit and a current source circuit is provided. The reference voltage generating circuit generates a first reference voltage according to a first current. The reference voltage generating circuit includes a native transistor device, and the first current flows through the native transistor device. The current source circuit is coupled to the reference voltage generating circuit. The current source circuit generates a reference current according to the first reference voltage. The current source circuit includes a cascode transistor circuit, and the reference current flows through the cascode transistor circuit. The cascode transistor circuit includes a low-voltage transistor device and a high-voltage transistor device coupled in series.

公开(公告)号：US20240385635A1

公开(公告)日：2024-11-21

申请号：US18505879

申请日：2023-11-09

Applicant: SK hynix Inc.

Inventor： Ji Hyo KANG ,  Sung Kwon LEE

IPC: G05F1/46 ,  G05F3/16 ,  H03F3/45

Abstract: A voltage generation circuit includes a global driver, a local driver, and a local voltage converter. The global driver changes the voltage level of a second voltage line based on the voltage levels of a first boundary voltage and a first voltage line and changes the voltage level of a fourth voltage line based on the voltage levels of a second boundary voltage and a third voltage line. The local driver adjusts the voltage levels of the first and third voltage lines based on the voltage levels of the second and fourth voltage lines. The local voltage converter generates an internal voltage having a voltage level between the voltage levels of the first and third voltage lines.

公开(公告)号：US11855619B2

公开(公告)日：2023-12-26

申请号：US16744110

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tzung-Yo Hung ,  Pin-Dai Sue ,  Chien-Chi Tien ,  Ting-Wei Chiang

IPC: H03K17/00 ,  H03K17/687 ,  H03K19/0948 ,  G05F3/16 ,  H03K19/0185 ,  H01L21/02 ,  H01L21/283 ,  H01L21/822 ,  H01L29/423 ,  H01L29/06 ,  B82Y10/00

CPC classification number: H03K17/6872 ,  G05F3/16 ,  H01L21/02104 ,  H01L21/283 ,  H01L21/822 ,  H01L29/0669 ,  H01L29/42312 ,  H03K19/018571 ,  H03K19/0948 ,  B82Y10/00

Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

公开(公告)号：US11831238B2

公开(公告)日：2023-11-28

申请号：US17744443

申请日：2022-05-13

Applicant: Delta Electronics, Inc.

Inventor： Zhengyu Ye ,  Xueliang Chang ,  Qinghua Su

IPC: H02M3/07 ,  G05F3/16 ,  H02M3/335 ,  H02M1/00

CPC classification number: H02M3/07 ,  G05F3/16 ,  H02M3/33523 ,  H02M1/0058

Abstract: A power conversion system includes a power conversion circuit and a start circuit. The power conversion circuit includes a first terminal, a second terminal, an output capacitor, at least one switch unit, a flying capacitor and a magnetic element. The flying capacitor is connected between the first terminal and the second terminal. The output capacitor is electrically connected with the first terminal or the second terminal. The start circuit is configured to control the power conversion circuit to pre-charge. A first terminal of the start circuit is electrically connected with the first terminal, and a second terminal of the start circuit is electrically connected with the second terminal. During a start process of the power conversion circuit, the at least one flying capacitor and the output capacitor are pre-charged by the start circuit.

公开(公告)号：US11789477B1

公开(公告)日：2023-10-17

申请号：US17901244

申请日：2022-09-01

Applicant: Analog Devices, Inc.

Inventor： Kevin R. Wrenner ,  Ruida Yun ,  Kenneth G. Richardson

IPC: G05F3/16 ,  G05F1/567 ,  G05F3/26

CPC classification number: G05F1/567 ,  G05F3/16 ,  G05F3/262

Abstract: Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.

公开(公告)号：US11619961B1

公开(公告)日：2023-04-04

申请号：US17645871

申请日：2021-12-23

Applicant: NXP USA, Inc.

Inventor： Stefano Pietri ,  John Pigott

IPC: G05F3/30 ,  G05F3/16

Abstract: A bandgap reference correction circuit comprising a bandgap reference circuit comprising a first resistor; a first oscillator comprising a second resistor, wherein a frequency of a first oscillator output signal of the first oscillator depends on a resistance of the second resistor; and a compensation module configured to: receive the first oscillator output signal from the first oscillator and a reference frequency signal from a reference oscillator; determine the frequency of the first oscillator output signal using the reference frequency signal; and set a resistance of the first resistor based on the frequency of the first oscillator output signal.

公开(公告)号：US20210218398A1

公开(公告)日：2021-07-15

申请号：US16744110

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TZUNG-YO HUNG ,  PIN-DAI SUE ,  CHIEN-CHI TIEN ,  TING-WEI CHIANG

IPC: H03K17/687 ,  H03K19/0948 ,  G05F3/16 ,  H03K19/0185 ,  H01L29/06 ,  H01L21/02 ,  H01L21/283 ,  H01L21/822 ,  H01L29/423

Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

公开(公告)号：US11016518B2

公开(公告)日：2021-05-25

申请号：US16217919

申请日：2018-12-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Yih-Shan Yang

IPC: G05F3/16 ,  G06F7/485 ,  H02M3/07

Abstract: A voltage subtracter includes a first charge storage device and a second charge storage device. The first charge storage device receives a first voltage and a second voltage during a first time period, and storages a first difference voltage between the first voltage and the second voltage. The second charge storage device receives a reference ground voltage and the first voltage during a second time period, and storages a second difference voltage between the reference ground voltage and the first voltage. The first charge storage device and the second charge storage device are coupled to an output end during a second time period, and a charge sharing operation is operatedon the first charge storage device and the second charge storage device to generate an output voltage on the output end.

公开(公告)号：US20200319661A1

公开(公告)日：2020-10-08

申请号：US16908784

申请日：2020-06-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Maciej Piotr JANKOWSKI ,  Peng CAO

IPC: G05F3/16 ,  G01R31/28

Abstract: A method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

公开(公告)号：US10794770B2

公开(公告)日：2020-10-06

申请号：US16277215

申请日：2019-02-15

Applicant: ABLIC INC. ,  The Ritsumeikan Trust

Inventor： Fumiyasu Utsunomiya ,  Takakuni Douseki ,  Ami Tanaka

IPC: H03F3/08 ,  G05F3/16 ,  G01J5/34 ,  G01R19/00 ,  H03K19/0944

Abstract: A signal detection circuit includes: a power terminal; a first current limitation circuit; a second current limitation circuit; a current-voltage conversion circuit; a first p-channel MOS transistor including a source, a gat, and a drain; a first n-channel MOS transistor including a drain, a gate, and a source; and a second n-channel MOS transistor in which a drain is connected to a first connection point connecting the resistor with the drain of the first n-channel MOS transistor, a gate is connected to a second connection point connecting the drain of the first p-channel MOS transistor with the current-voltage conversion circuit, and a source is grounded.