-
公开(公告)号：US11966247B1
公开(公告)日：2024-04-23
申请号：US18160536
申请日：2023-01-27
Applicant: pSemi Corporation
Inventor： Rogelio Cicili
Abstract: Methods and devices for a wide-swing cascode current mirror with low headroom voltage and high output impedance are presented. An input leg of the current mirror includes a composite transistor in series connection with an intrinsic transistor. The composite transistor includes two series-connected regular transistors with respective sizes that are twice the size of the intrinsic transistor. An output leg of the current mirror includes a regular transistor in series connection with an intrinsic transistor. A gate voltage of the composite transistor, provided at a node that is common to gates of the two series-connected regular transistors, self-establishes when a reference current flows through the input leg. The self-established gate voltage is used to bias the regular transistor of the output leg. Biasing voltages to gates of the intrinsic transistors is provided by an intermediate node that provides the series connection of the regular transistors of the composite transistor.
-
公开(公告)号：US11934609B2
公开(公告)日：2024-03-19
申请号：US17301080
申请日：2021-03-24
Applicant: Microchip Technology Incorporated
Inventor： Lei Zou
CPC classification number: G06F3/04166 , G05F3/205 , G05F3/262
Abstract: One or more embodiments relate to a multi-bias mode current conveyor. Such a current conveyor may include an input terminal, a reference terminal, an output terminal, a first and second cascoded current mirrors, and a biasing circuit. The first cascoded current mirror and a second cascoded current mirror may be arranged as a current conveyor that is configured to provide an output current that a mirror of an input current. The biasing circuit may be configured to provide a bias voltage selectively exhibiting a first voltage level or a second voltage level. The bias voltage may be provided at least partially responsive to a state of the input current. The biasing circuit may be arranged to apply the bias voltage to at least one of the first cascoded current mirror or the second cascoded current mirror.
-
公开(公告)号：US11846962B2
公开(公告)日：2023-12-19
申请号：US17740589
申请日：2022-05-10
Applicant: Infineon Technologies AG
Inventor： Mario Motz , Francesco Polo
CPC classification number: G05F3/267 , G05F3/20 , G05F3/22 , G05F3/26 , H03F3/45475
Abstract: A bandgap reference circuit includes a bandgap reference core circuit that includes a first bipolar transistor having a first emitter current density and a first base-emitter voltage, a second bipolar transistor having a second emitter current density that is smaller than the first emitter current density and having a second base-emitter voltage, a resistor that is connected to the emitter of the second bipolar transistor, and a differential amplifier circuit that is configured to control first and second emitter currents through the first and second bipolar transistors, respectively, such that a sum of the second base-emitter voltage and a voltage drop across the resistor approximates the first base-emitter voltage. The bandgap reference circuit further includes a first replica bipolar transistor that emulates an operating point of the first bipolar transistor and a second replica bipolar transistor that emulates an operating point of the second bipolar transistor.
-
4.发明授权公开(公告)号：US11791834B2
公开(公告)日：2023-10-17
申请号：US17672378
申请日：2022-02-15
Inventor： Yu-Jie Huang , Mu-Shan Lin , Chien-Chun Tsai
Abstract: A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.
-
公开(公告)号：US20230283243A1
公开(公告)日：2023-09-07
申请号：US18172008
申请日：2023-02-21
Applicant: Infineon Technologies AG
Inventor： Herwig Wappis , Peter Singerl , Martin Mataln , Gerhard Maderbacher
CPC classification number: H03F1/302 , G05F3/205 , H03F1/0266
Abstract: A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.
-
Patent Agency Ranking
公开(公告)号：US11579645B2
公开(公告)日：2023-02-14
申请号：US16448538
申请日：2019-06-21
Applicant: Wolfspeed, Inc.
Inventor： James Richmond , Edward Robert Van Brunt , Philipp Steinmann
Abstract: A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.
-
公开(公告)号：US11469753B1
公开(公告)日：2022-10-11
申请号：US17365201
申请日：2021-07-01
Inventor： Hamed Sadati , Yu Tamura
Abstract: A switching driver circuit may have an output stage having an output switch connected between a switching voltage node and an output node. A switch network may control a switching voltage at the switching voltage node so that in one mode the switching voltage node is coupled to a positive voltage and in another mode the switching voltage node is coupled to ground voltage via a first switching path of the switch network. The circuit may also include an n-well switching block operable to, when the first switching voltage node is coupled to a positive voltage, connect the n-well of the first output switch to the switching voltage node, and, when the first switching voltage node is coupled to the ground voltage, connect the n-well of the first output switch to a first ground which is separate to the first switching voltage node and independent of the first switching path.
-
8.发明申请公开(公告)号：US20220128833A1
公开(公告)日：2022-04-28
申请号：US17182305
申请日：2021-02-23
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yo Sub MOON
Abstract: An apparatus with hall sensor common mode voltage adjustment includes: a bias provider configured to provide a bias current to the hall sensor; a first voltage regulator configured to vary a first voltage difference between the hall sensor and the bias provider, based on the bias current; and a second voltage regulator configured to vary a second voltage difference between the hall sensor and a ground, based on the bias current. The first and second voltage differences are variable such that a difference between the first voltage difference and the second voltage difference corresponds to a difference between a common mode voltage of first and second hall sensor output terminals of the hall sensor and a reference voltage.
-
公开(公告)号：US20210286394A1
公开(公告)日：2021-09-16
申请号：US16819088
申请日：2020-03-14
Applicant: Vidatronic, Inc.
Inventor： Mohammad Ahmed RADWAN , Anand Veeravalli RAGHUPATHY , Michael A NIX
Abstract: A current reference circuit with one or more current mirror devices having dynamic body biasing includes a voltage-to-current converter circuit having a feedback loop that includes an operational amplifier, an NMOS device, and a resistor to generate a reference current; a current mirror circuit, including one or more current mirror devices with source degeneration, to produce one or more output currents that are copies of the reference current; and a body-biasing stage including an active N-well to dynamically set a body-biasing voltage for the one or more current mirror devices.
-
10.发明申请公开(公告)号：US20210247793A1
公开(公告)日：2021-08-12
申请号：US17181950
申请日：2021-02-22
Applicant: Apple Inc.
Inventor： Seyedeh Sedigheh Hashemi , Vahid Majidzadeh Bafar , Ali Mesgarani , Mansour Keramat
IPC: G05F3/26 , G05F3/20 , G11C11/4074 , G11C5/14
Abstract: A power detect circuit is disclosed. A power detect circuit includes a voltage multiplier that receives an external supply voltage and generates a second supply voltage that is greater than the former. A voltage regulator is coupled to receive the second supply voltage and outputs a regulated supply voltage. A bandgap circuit is coupled to receive the second supply voltage when a first switch is closed, and the regulated supply voltage when a second switch is closed. The bandgap circuit generates a reference voltage for the voltage regulator, as well as one or more output voltages. A comparator circuit is coupled to receive the one or more output voltages from the bandgap circuit, and may compare these one or more output voltages to the regulated supply voltage.
-
-
-
-
-
-
-
-
-
Search Results
1089
records
(took 0.024 seconds)
