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公开(公告)号：US20240361794A1
公开(公告)日：2024-10-31
申请号：US18309340
申请日：2023-04-28
摘要： In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.
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公开(公告)号：US20240361791A1
公开(公告)日：2024-10-31
申请号：US18139786
申请日：2023-04-26
发明人： Federico MUSARRA , Sandor PETENYI
摘要： An electronic device includes multiple integrated circuits, each containing a power transistor connected between an input voltage node and a load node, as well as a regulation circuit generating at least one sense current representing the output current of the power transistor. The regulation circuits modulate the output currents of their power transistors based on a value derived from the sense currents generated by the regulation circuits of other integrated circuits. This derived value can be based on an average of the sense currents generated by the regulation circuits or on one of the sense currents. In particular, the integrated circuits can be arranged in a daisy-chained relationship, allowing each regulation circuit to compare its sense current with the one from the immediately preceding circuit, except for the first regulation circuit, which compares its sense current with the last circuit's sense current in the chain.
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公开(公告)号：US12130650B2
公开(公告)日：2024-10-29
申请号：US17882896
申请日：2022-08-08
发明人： Kuan-Hung Chen
CPC分类号： G05F3/24
摘要： A start-up circuit includes series-connected first-type first transistors through which a start-up current flows in a start-up period, being connected between a positive power voltage and an inner node; and a first-type second transistor through which a boost current flows in the start-up period, being connected between the positive power voltage and the inner node, and with a gate connected to an output node that provides a bias voltage.
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公开(公告)号：US20240321877A1
公开(公告)日：2024-09-26
申请号：US18614055
申请日：2024-03-22
发明人： Yasuo Matsumura
IPC分类号： H01L27/088 , G05F1/46 , G05F3/24 , H01L21/8236 , H01L27/06
CPC分类号： H01L27/0883 , G05F1/468 , G05F3/242 , H01L21/8236 , H01L27/0629
摘要： A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.
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公开(公告)号：US20240295894A1
公开(公告)日：2024-09-05
申请号：US18663832
申请日：2024-05-14
申请人： KIOXIA CORPORATION
发明人： Koji OOIWA
CPC分类号： G05F3/24 , G06F13/1668 , G11C16/0483
摘要： According to one embodiment, a voltage generation circuit includes a voltage dividing circuit, a first current path, a second current path, a first output terminal, a second output terminal, and a switching circuit. The first current path is in parallel with the voltage dividing circuit between a first node connected to a power source line and a second node. The second current path is in parallel with the voltage dividing circuit between a third node and a fourth node. The first output terminal is connected to the second node. The second output terminal is connected to the third node. The switching circuit is configured to switch connection of the first current path and the second current path. The first node, the second node, the third node, and the fourth node are connected in series in the voltage dividing circuit.
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公开(公告)号：US20240201723A1
公开(公告)日：2024-06-20
申请号：US18082942
申请日：2022-12-16
发明人： Nishant Singh THAKUR
摘要： An apparatus comprising a bias current generator for generating a bias current, the bias current generator comprising two or more negative threshold transistors of the same type and coupled in series.
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公开(公告)号：US20240134407A1
公开(公告)日：2024-04-25
申请号：US18403965
申请日：2024-01-04
IPC分类号： G05F3/26 , G01R19/165 , G05F3/24 , G06F1/28 , H03K17/30
CPC分类号： G05F3/262 , G01R19/16533 , G01R19/16566 , G05F3/247 , G06F1/28 , H03K17/302
摘要： A voltage supervisor includes a first transistor coupled between a first supply voltage and a second supply voltage. The voltage supervisor includes a second transistor coupled between the first supply voltage and the second supply voltage. The voltage supervisor is configured to provide a first current proportional to a difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is also configured to provide a second current proportional to a difference in the first supply voltage and the difference in gate-to-source voltages of the first transistor and the second transistor. The voltage supervisor is configured to compare the first current to the second current to determine a voltage value that changes a state responsive to the first supply voltage crossing a threshold.
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公开(公告)号：US11953928B2
公开(公告)日：2024-04-09
申请号：US17287465
申请日：2019-09-26
申请人： Sciosense B.V.
摘要： In an embodiment an electric circuit arrangement includes a current generator circuit having a first output terminal and configured to generate an output current, a controller configured to generate control signals to control the current generator circuit, a random code generator configured to generate random codes and a counter configured to generate a count, wherein the current generator circuit comprises a plurality of output current paths and a plurality of controllable switching circuits, wherein each of the output current paths includes a respective electrical component to define a current in the respective output current path, wherein a respective one of the controllable switching circuits is coupled to a respective one of the output current paths to connect the respective electrical component to the first output terminal, and wherein the random code generator is configured to provide a respective code derived from a respective one of the random codes.
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公开(公告)号：US11867570B2
公开(公告)日：2024-01-09
申请号：US17192438
申请日：2021-03-04
发明人： Philippe Galy , Renan Lethiecq
IPC分类号： G01K7/01 , G01K7/22 , G01K7/25 , H01L27/12 , H01C7/04 , G05F3/24 , H01C7/00 , H01L29/10 , H01L29/78
CPC分类号： G01K7/01 , G01K7/015 , G01K7/22 , G01K7/226 , G01K7/25 , G05F3/245 , H01C7/008 , H01C7/04 , H01L27/1203 , H01L29/1095 , H01L29/7831
摘要： An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal imposes the drain-source current of the first transistor.
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公开(公告)号：US11829174B2
公开(公告)日：2023-11-28
申请号：US17395335
申请日：2021-08-05
申请人： SK hynix Inc.
摘要： Disclosed herein is a regulator for a non-volatile memory. The regulator comprises a high voltage supply terminal, a low voltage supply terminal, an output terminal, a ground terminal and an internal node. The regulator further comprises an input amplifier inserted between the low voltage supply terminal and the ground terminal and outputting a first output voltage at a first intermediate output node according to a reference voltage and a feedback voltage provided at its negative and positive input terminals, respectively; a mirror circuit forming two current paths between the internal node and the ground terminal and between the internal node and a second intermediate output node respectively; and a cascode block coupled between the high voltage supply terminal and the internal node and operating in response to a voltage at the second intermediate output node of the regulator where the two current path is formed by the mirror circuit.
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