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1.发明申请公开(公告)号：US20230131079A1
公开(公告)日：2023-04-27
申请号：US17913454
申请日：2021-03-26
申请人： DSPACE GMBH
发明人： Dominik Lubeley , Marc Schlenger , Paul Gruber
摘要： A method for inputting and/or outputting signals having a selectable sample rate in a time-synchronized manner on a group of input and/or output channels of an electronic circuit includes: configuring each channel of the group at a standard sample period; synchronously initiating all the channels of the group at the standard sample period; detecting an entry for a modified sample period TPeriod of a first channel of the group; detecting a current counter value TCounter; configuring the first channel at the modified sample period; establishing a waiting time of TWaiting clocks in accordance with TWaiting=TPeriod−mod(TCounter, TPeriod), where mod(TCounter, TPeriod) denotes the division remainder from the current counter value TCounter and the modified sample period TPeriod; and initiating the first channel after the waiting time TWaiting.
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公开(公告)号：US11619965B2
公开(公告)日：2023-04-04
申请号：US17950808
申请日：2022-09-22
申请人： Magic Leap, Inc.
发明人： Niv Margalit , Eyal Sela
摘要： An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.
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公开(公告)号：US11595405B2
公开(公告)日：2023-02-28
申请号：US17843307
申请日：2022-06-17
申请人： Itron, Inc.
发明人： Bernard M. Woodland
摘要： A method for synchronizing time may include receiving initial time information including an initial timestamp from a first device, adjusting a clock of the device with the initial time information, storing the initial time information as an earliest possible time, receiving additional time information, including a second timestamp, from a second device, and evaluating the additional time information. When the evaluated additional time information includes information that is unacceptable, the method may further include adjusting the clock with the second timestamp, and replacing the earliest possible time with the second timestamp. When the evaluated additional time information includes information that is acceptable, the method may further include adjusting the clock with the additional time information, and replacing the earliest possible time with the additional time information. The initial time information and additional time information may be respectively determined based on reconciled time data received from two or more proximate devices.
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公开(公告)号：US11569728B1
公开(公告)日：2023-01-31
申请号：US17456848
申请日：2021-11-29
发明人： Winand Van Sloten , Filippo Boera
摘要： A circuit for controlling a switch of a power converter includes a first clock signal generator configured to generate a first clock signal and a switching signal generator configured to generate a switching signal to control the switch of the power converter based on the first clock signal. The circuit further includes error detection circuitry configured to output an error indication and a second clock signal generator configured to generate, in response to the error indication, a second clock signal that comprises an edge of a clock cycle of the second clock signal that corresponds to when the switching signal deactivates the switch of the power converter plus a time delay. The switching signal generator is configured to generate the switching signal to control the switch of the power converter further based on the second clock signal in response to the error indication being output by the error detection circuitry.
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公开(公告)号：US11561600B2
公开(公告)日：2023-01-24
申请号：US17000750
申请日：2020-08-24
发明人： Young-Pyo Joo , Taek-Kyun Shin
IPC分类号： G06F1/00 , G06F1/324 , G06F1/20 , G06F1/3212 , G06F1/06 , G06F1/26 , G06F1/3234 , G06F1/3287
摘要： An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.
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公开(公告)号：US20230018203A1
公开(公告)日：2023-01-19
申请号：US17950808
申请日：2022-09-22
申请人： Magic Leap, Inc.
发明人： Niv MARGALIT , Eyal SELA
摘要： An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.
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公开(公告)号：US20230014288A1
公开(公告)日：2023-01-19
申请号：US17648806
申请日：2022-01-24
发明人： Yuanyuan SUN
摘要： A staggering signal generation circuit includes a pulse generation circuit, a counting circuit and a signal generation circuit. The pulse generation circuit generates a first periodic pulse signal and a second periodic pulse signal; the counting circuit counts the first periodic pulse signal and the second periodic pulse signal to generate rising edge triggering signals and falling edge triggering signals; and the signal generation circuit generate a staggering pulse signal according to the input rising edge triggering signals and the input falling edge triggering signals.
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公开(公告)号：US11537547B2
公开(公告)日：2022-12-27
申请号：US17174573
申请日：2021-02-12
发明人： Chi-Yung Sun
摘要： A slave device coupled to a master device via a bus and including a serial interface, a code generator circuit, and a control circuit is provided. The serial interface is configured to be coupled to the bus. The code generator circuit is configured to generate a unique code. The control circuit is coupled between the serial interface and the code generator circuit. In a set mode, the control circuit triggers the code generator circuit to generate the unique code. In an operation mode, the control circuit determines whether to perform commands provided by the master device according to the unique code.
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公开(公告)号：US11526193B2
公开(公告)日：2022-12-13
申请号：US16295255
申请日：2019-03-07
摘要： In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.
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公开(公告)号：US11520628B2
公开(公告)日：2022-12-06
申请号：US16878974
申请日：2020-05-20
发明人： Hee Jun Park
摘要： In a real-time system having first and second processor systems, cooperative dynamic clock and voltage scaling (“DCVS”) may include a first processor system monitoring a condition indicative of first processor workload, adjusting a first processor operating frequency in response to a detected amount of change in the first processor workload, and providing an indication based on the detected amount of change in the first processor workload to the second processor contemporaneously with providing first processor output data to the second processor. The cooperative DCVS may further include the second processor system adjusting a second processor operating frequency in response to the indication.
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