Electronics module for a wearable device

    公开(公告)号:US12130686B2

    公开(公告)日:2024-10-29

    申请号:US18307198

    申请日:2023-04-26

    CPC分类号: G06F1/3215 G06F1/3231

    摘要: The electronics module 100 comprises a controller 103. The controller 103 is arranged to operate in a first power mode and a second power mode. The first power mode consumes less power than the second power mode. The controller 103 is arranged to transition from the first power mode to the second power mode in response to an input unit of the electronics module 100 detecting an input event. In the second power mode, the controller 103 is arranged to receive a signal from a sensing unit of the wearable article, determine from the signal whether the wearable article is being worn. In response to determining that the wearable article is not being worn, the controller 103 is arranged to transition from the second power mode to the first power mode.

    Real-time power meter for optimizing processor power management

    公开(公告)号:US12124350B2

    公开(公告)日:2024-10-22

    申请号:US16860967

    申请日:2020-04-28

    申请人: Intel Corporation

    摘要: A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.

    Preserving a decoupling capacitor's charge during low power operation of a logic circuit

    公开(公告)号:US12099394B2

    公开(公告)日:2024-09-24

    申请号:US17805652

    申请日:2022-06-06

    申请人: NXP B.V.

    CPC分类号: G06F1/3212 G06F1/3296

    摘要: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

    Low-power vision sensing
    6.
    发明授权

    公开(公告)号:US12093114B2

    公开(公告)日:2024-09-17

    申请号:US17777968

    申请日:2020-12-16

    申请人: Google LLC

    摘要: Methods, systems, and apparatus, for performing low-power vision sensing. One computing device includes a vision sensor configured to generate vision sensor data and an ambient computing system configured to repeatedly process the vision sensor data generated by the vision sensor according to a low-power detection process. If a detection is indicated by the low-power detection process, the ambient computing system wakes one or more other components of the computing device to perform a high-power detection process using the vision sensor data.

    Power control systems and methods for machine learning computing resources

    公开(公告)号:US12079063B2

    公开(公告)日:2024-09-03

    申请号:US18207297

    申请日:2023-06-08

    CPC分类号: G06F1/3287 G06F1/3296

    摘要: Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.

    Method and system for providing power saving in computer systems

    公开(公告)号:US12079062B2

    公开(公告)日:2024-09-03

    申请号:US18048661

    申请日:2022-10-21

    发明人: Yung-Fu Li

    摘要: A system and method to save power in a computer system is disclosed. The system includes a power controller controlling connection of power to each of a plurality of memory components. A processor is coupled to the memory components. The processor operates with varying utilization levels of the memory components. A management controller is coupled to the processor and the power controller. The management controller determines a period of low utilization based on memory utilization data from the processor. The management controller commands the power controller to disable power to some of the plurality of memory components during the period of low utilization.