Automated network-on-chip design
    1.
    发明授权

    公开(公告)号:US11544441B2

    公开(公告)日:2023-01-03

    申请号:US16274173

    申请日:2019-02-12

    发明人: Wolfgang Fink

    摘要: Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.

    Method for reservoir simulation optimization under geological uncertainty

    公开(公告)号:US11543560B2

    公开(公告)日:2023-01-03

    申请号:US17047131

    申请日:2019-04-15

    发明人: Kashif Rashid

    摘要: A method, computer program product, and computing system are provided for receiving reservoir data associated with the reservoir. A simulation may be performed on the reservoir data to generate simulated reservoir data. A subset of realizations including a minimal number of realizations from a plurality of realizations may be determined based upon, at least in part, one or more statistical moments of the simulated reservoir data. An optimized reservoir model associated with an objective may be generated based upon, at least in part, the subset of realizations including the minimal number of realizations.

    Analyzing delay variations and transition time variations for electronic circuits

    公开(公告)号:US11288426B2

    公开(公告)日:2022-03-29

    申请号:US17019577

    申请日:2020-09-14

    申请人: Synopsys, Inc.

    摘要: A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing an asymmetric distribution of delay values and generates a normal distribution of delay values. The system receives measures of nominal transition time at an output and input of a wire, and transition time variation at the input of the wire and determines a transition time variation at the output of the wire. The system receives measures of an Elmore delay and a nominal delay of the wire and determines a delay variation at the output of the wire.

    System and method for estimation of chip floorplan activity

    公开(公告)号:US11100269B2

    公开(公告)日:2021-08-24

    申请号:US16579836

    申请日:2019-09-24

    申请人: ARTERIS, INC.

    摘要: Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.

    Method and system for formal bug hunting

    公开(公告)号:US11080448B1

    公开(公告)日:2021-08-03

    申请号:US16910815

    申请日:2020-06-24

    摘要: A method for formal deep bug hunting in a device under test (DUT) may include obtaining a selection of a start state for the DUT; obtaining a selection of one or a plurality of variables that are declared as random variables; for each of said one or a plurality of random variables, generating a sequence of random values in a generation order using a random number generator (RNG); and performing formal verification exploration of the DUT starting at the start state and consecutively assigning each of said one or a plurality of random variables a value from the sequence of values in the generation order.

    Generation of isotherm datasets for reservoir volumetric estimation

    公开(公告)号:US10705250B2

    公开(公告)日:2020-07-07

    申请号:US14328374

    申请日:2014-07-10

    摘要: A computer-implemented method for reservoir volumetric estimation, a non-transitory computer-readable medium, and a computing system. The method may include running a molecular dynamics simulation of a fluid-rock model of a first reservoir system at a plurality of pressures. The fluid-rock model includes a fluid that is at least partially adsorbed in the first reservoir system at one or more pressures of the plurality of pressures. The method may also include calculating a plurality of isothermal density profiles of the fluid in the first reservoir system, in association with the plurality of pressures using a result of the molecular dynamics simulation. The method may further include determining a first gas accumulation of the fluid in the first reservoir system for the plurality of isothermal density profiles. The first gas accumulation is at least partially a function of a pore surface area of a sample of the first reservoir system.

    Space exploration with Bayesian inference

    公开(公告)号:US10678971B2

    公开(公告)日:2020-06-09

    申请号:US16040834

    申请日:2018-07-20

    摘要: A system, a computer program product, and method for physically fabricating an electronic circuit using design space exploration as part of a design process is described. The method begins with defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters. Next an output target to be optimized is defined. A series of one or more test mask shapes are generated to appear on a photo mask using the plurality of design space parameters. A simulation of a post lithography or etch on the series of one or more test mask shapes is performed to produce simulation output values. Next, the simulation output values and corresponding design space parameters are fed into to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate.