公开(公告)号：US12235772B2

公开(公告)日：2025-02-25

申请号：US18463256

申请日：2023-09-07

Applicant: Daedalus Cloud LLC

Inventor： Xavier Aldren Simmons ,  Jack Spencer Turpitt ,  Rafael John Patrick Shuker ,  Tyler Wilson Hale ,  Alexander Kingsley St. John ,  Stuart John Inglis

IPC: G06F9/30 ,  G06F3/06 ,  G06F9/38 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0815 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14

Abstract: A method comprising: receiving, at a vector processor, a request to store data; performing, by the vector processor, one or more transforms on the data; and directly instructing, by the vector processor, one or more storage device to store the data; wherein performing one or more transforms on the data comprises: erasure encoding the data to generate n data fragments configured such that any k of the data fragments are usable to regenerate the data, where k is less than n; and wherein directly instructing one or more storage device to store the data comprises: directly instructing the one or more storage devices to store the plurality of data fragments.

公开(公告)号：US12216591B2

公开(公告)日：2025-02-04

申请号：US18477674

申请日：2023-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

公开(公告)号：US12216589B2

公开(公告)日：2025-02-04

申请号：US18044499

申请日：2021-08-16

Applicant: Arm Limited

Inventor： Wei Wang ,  Matthew James Horsnell

IPC: G06F12/12 ,  G06F9/46 ,  G06F9/52 ,  G06F12/0862 ,  G06F12/0897

Abstract: An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.

公开(公告)号：US20250028652A1

公开(公告)日：2025-01-23

申请号：US18909000

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: A caching system including a first sub-cache, and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes line type bits configured to store an indication that a corresponding line of the second sub-cache is configured to store write-miss data.

公开(公告)号：US12189540B2

公开(公告)日：2025-01-07

申请号：US18456619

申请日：2023-08-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/12 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F12/128 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.

公开(公告)号：US20240419523A1

公开(公告)日：2024-12-19

申请号：US18821283

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Shakeel Isamohiuddin BUKHARI ,  Mark ISH

IPC: G06F11/00 ,  G06F12/02 ,  G06F12/12

Abstract: In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.

公开(公告)号：US20240403206A1

公开(公告)日：2024-12-05

申请号：US18493144

申请日：2023-10-24

Applicant: SK hynix Inc.

Inventor： Hyeong Jae CHOI ,  Seung Soo KIM ,  Chi Je PARK

IPC: G06F12/02 ,  G06F12/12

Abstract: The present disclosure relates to a storage device capable of receiving early suspend information from an external device (e.g., host) and performing an appropriate operation during a power saving mode for an application installed on the external device, and a method of operating a memory controller of the storage device. The method of operating a memory controller may include: receiving early suspend information from an external device; and controlling a background operation according to the reception of the early suspend information. The background operation refers to an operation that is performed internally regardless of a request from the external device.

公开(公告)号：US12141601B2

公开(公告)日：2024-11-12

申请号：US18456568

申请日：2023-08-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson ,  Neelima Muralidharan

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/121 ,  G06F13/16

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

公开(公告)号：US20240345740A1

公开(公告)日：2024-10-17

申请号：US18453313

申请日：2023-08-22

Applicant: SK hynix Inc.

Inventor： Byoung Min JIN ,  Ku Ik KWON ,  Gyu Yeul HONG

IPC: G06F3/06 ,  G06F12/12

CPC classification number: G06F3/0617 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0673 ,  G06F12/12

Abstract: The storage device may receive a condition for a down-time mode from the host. The storage device may cache, when the condition for the down-time mode is determined as satisfied, at least a part of update data units in the update cache. The storage device may process a read command received from the host in the down-time mode based on update data units cached in the update cache.

公开(公告)号：US20240338323A1

公开(公告)日：2024-10-10

申请号：US18295866

申请日：2023-04-05

Applicant: Arm Limited

Inventor： Eric Ola Harald LILJEDAHL ,  Jatin BHARTIA

IPC: G06F12/12 ,  G06F12/0891

CPC classification number: G06F12/12 ,  G06F12/0891

Abstract: An apparatus with an additional storage element or field is provided where a subscription indicator is stored, indicating a subscription to a region of memory, and hence subscribing to a cache line corresponding to the region of memory. In response to a subscribed cache line being invalidated, the apparatus performs actions to re-fetch the cache line, and to store the cache line in the cache after a short delay. The subscription indicator may be stored in a variety of ways, and may include further information that influences the functionality of the present techniques. Such further information may be adjustable in order to dynamically control the functionality of the disclosed techniques for a particular implementation over time.