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公开(公告)号：US20250068577A1
公开(公告)日：2025-02-27
申请号：US18812672
申请日：2024-08-22
Applicant: Alibaba Innovation Private Limited
Inventor： Yijin GUAN , Dimin NIU , Tianchan GUAN , Zhaoyang DU , Hongzhong ZHENG
Abstract: The present invention provides a switch, which is equipped with multiple connection interfaces, for connecting to multiple external processors respectively, enabling mutual access to the respective memories of these processors through the switch. The switch is configured to: through a memory request service component corresponding to a first processor, set within the switch, receive a first memory request sent by the first processor; convert the first memory request into a second memory request aimed at accessing the memory of a second processor and send this second memory request to a memory response service component corresponding to the second processor within the switch; through the memory response service component, convert the second memory request into a third memory request for accessing local memory and send this third memory request to the second processor to access the memory resources corresponding to the second processor.
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公开(公告)号：US20250068574A1
公开(公告)日：2025-02-27
申请号：US18454658
申请日：2023-08-23
Applicant: QUALCOMM Incorporated
Inventor： Jungwon Suh , Pankaj Deshmukh , Subbarao Palacharla , Alain Artieri
IPC: G06F13/16 , G06F1/3234 , G06F13/28
Abstract: This disclosure provides systems, methods, and devices for memory systems that support an efficient mode for reducing power consumption in a memory module while maintaining access to all contents of memory. In a first aspect, a method includes communicating, by a memory module, first data stored in a first plurality of banks to a host device through a first sub-channel in a first operating mode; communicating second data stored in the second plurality of banks to the host device through a second sub-channel in the first operating mode; receiving a command to enter a second operating mode; and communicating third data stored in the first plurality of banks and fourth data stored in the second plurality of banks to the host device through the first sub-channel in the second operating mode. Other aspects and features are also claimed and described.
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公开(公告)号：US20250068573A1
公开(公告)日：2025-02-27
申请号：US18943232
申请日：2024-11-11
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Wenjie MU , Jiawei CHEN , Shu XIE
IPC: G06F13/16
Abstract: A memory device includes a memory array including a first memory plane and a second memory plane, and a peripheral circuit coupled to the memory array and configured to perform an operation. The operation includes receiving a first instruction and input data, and in response to the first instruction, writing first data of the input data to the first memory plane and second data of the input data to the second memory plane. The second data is configured to indicate whether the first data has been performed with an inversion operation prior to transmission.
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公开(公告)号：US20250068572A1
公开(公告)日：2025-02-27
申请号：US18949354
申请日：2024-11-15
Applicant: Micron Technology, Inc.
Inventor： Bryan Hornung , Tony M. Brewer , Douglas Vanesko , Patrick Estep
Abstract: Linear interpolation is performed within a memory system. The memory system receives a floating-point point index into an integer-indexed memory array. The memory system accesses the two values of the two adjacent integer indices, performs the linear interpolation, and provides the resulting interpolated value. In many system architectures, the critical limitation on system performance is the data transfer rate between memory and processing elements. Accordingly, reducing the amount of data transferred improves overall system performance and reduces power consumption.
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公开(公告)号：US20250068571A1
公开(公告)日：2025-02-27
申请号：US18940938
申请日：2024-11-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： INSOON JO
Abstract: An operating method of an electronic device which includes a processor and a memory, the method including: accessing, using the processor, the memory without control of an external host device in a first bias mode; sending, from the processor, information of the memory to the external host device when the first bias mode ends; and accessing, using the processor, the memory under control of the external host device in a second bias mode.
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Patent Agency Ranking
公开(公告)号：US20250061068A1
公开(公告)日：2025-02-20
申请号：US18940613
申请日：2024-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Oscar P. Pinto , Robert Brennan
IPC: G06F13/16
Abstract: Embodiments of the present invention include a drive-to-drive storage system comprising a host server having a host CPU and a host storage drive, one or more remote storage drives, and a peer-to-peer link connecting the host storage drive to the one or more remote storage drives. The host storage drive includes a processor and a memory, wherein the memory has stored thereon instructions that, when executed by the processor, causes the processor to transfer data from the host storage drive via the peer-to-peer link to the one or more remote storage drives when the host CPU issues a write command.
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公开(公告)号：US12231537B2
公开(公告)日：2025-02-18
申请号：US17190027
申请日：2021-03-02
Applicant: Kioxia Corporation
Inventor： Taichi Ejiri
Abstract: A memory system includes a nonvolatile memory and a controller. In a case where first encrypted data obtained by encrypting first data with a first DEK is stored in the nonvolatile memory, in response to determining that second data received based on a first write request from a host is the same as the first data and a first user uses the host, the controller encrypts the first DEK with a first KEK associated with the first user to acquire a first encrypted DEK, and stores the first encrypted DEK.
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公开(公告)号：US12230232B2
公开(公告)日：2025-02-18
申请号：US17818613
申请日：2022-08-09
Applicant: Micron Technology, Inc.
Inventor： Giuseppe Cariello
Abstract: Methods, systems, and devices for configurable types of write operations are described. A memory device may receive a write command to write data in a zone of a memory system. The memory device may identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command. In some examples, the cursor may be associated with a type of a write operation based on a quantity of data associated with the cursor. As such, the memory device write, using a first type of the write operation or a second type of the write operation in accordance with the quantity of data, the data, and an indication of the type of the write operation used to write the data into the memory system.
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公开(公告)号：US12229444B2
公开(公告)日：2025-02-18
申请号：US17892960
申请日：2022-08-22
Applicant: Micron Technology, Inc.
Abstract: Methods, systems, and devices for command scheduling for a memory system are described. A memory system may be configured to analyze a received command during an initialization procedure for one or more components. In some examples, the memory system may initialize an interface and one or more processing elements as part of an initialization procedure upon transitioning from a first power mode to a second power mode. Accordingly, the command may be analyzed while the processing elements are being initialized such that, upon the processing elements being fully initialized, the command may be processed (e.g., executed).
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公开(公告)号：US12229435B2
公开(公告)日：2025-02-18
申请号：US18412731
申请日：2024-01-15
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Eric Linstadt , Torsten Partsch
IPC: G06F3/06 , G06F13/16 , G11C7/06 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4096 , H01L25/065
Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.
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