公开(公告)号：US20250061065A1

公开(公告)日：2025-02-20

申请号：US18781989

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Melky Arputharaja Siluvainathan

IPC: G06F13/12 ,  G06F13/24

Abstract: A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.

公开(公告)号：US20250053523A1

公开(公告)日：2025-02-13

申请号：US18932094

申请日：2024-10-30

Applicant: Lutron Technology Company LLC

Inventor： Andrew Karl Cooney ,  Devin N. Malanaphy ,  Matthew J. Price ,  Scott E. Shaw ,  Derek Thrasher

IPC: G06F13/16 ,  G06F13/24 ,  G06F13/28

Abstract: A control device may include a processor may include a core, a timer peripheral, and a peripheral direct memory access controller. The processor may include a receive port coupled to a communication port of the reporting device via a communication line. The control device may include a timer peripheral that can generate an enable signal and a timing signal, and a buffer circuit that may include an enable port for the enable signal for enabling/disabling the buffer circuit, an input port for the timing signal, and an output port coupled to the communication line. The processor may enable/disable the buffer circuit to control the timing of data bit(s) transmission across the communication line by the reporting device. The peripheral direct memory access controller may store the data bit(s) in a receive buffer during the bit period, and the core may subsequently retrieve the data bit(s) from the receiver buffer.

公开(公告)号：US12182042B2

公开(公告)日：2024-12-31

申请号：US17760328

申请日：2021-02-05

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Hiroo Takahashi ,  Makoto Nariya ,  Tadaaki Yuba

IPC: G06F13/24 ,  G06F13/42

Abstract: A transmission device according to an aspect of the present disclosure communicates with a reception device via a control data bus. The transmission device includes a generation unit that generates an interrupt request, and a transmission section that transmits data to the reception device via the control data bus. The interrupt request includes at least an identification bit to identify a type of transmission data, an information bit for the transmission data, and the transmission data.

公开(公告)号：US20240419586A1

公开(公告)日：2024-12-19

申请号：US18724093

申请日：2023-03-24

Applicant: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.

Inventor： Xingyuan LI ,  Jiang WANG ,  Huajin SUN ,  Shuqing LI

IPC: G06F12/02 ,  G06F13/24 ,  G06F13/42

Abstract: Disclosed are a method, system and apparatus for data transmission, and a storage medium, which relate to the field of data transmission, and are used for transmitting data. Address mapping logic is provided in a storage array card, and a host maps a storage address space thereof to the storage array card by the address mapping logic of the storage array card; and after a data transmission instruction is sent to an NVMeSSD by a hard disk control mapping address in the storage array card, the NVMeSSD can directly perform data transmission on the basis of the data transmission instruction and a host storage mapping address in the storage array card, that is, the NVMeSSD can directly perform data transmission with the storage address space inside the host.

公开(公告)号：US20240403247A1

公开(公告)日：2024-12-05

申请号：US18203434

申请日：2023-05-30

Applicant: NXP B.V.

Inventor： Robert Anthony McGowan

IPC: G06F13/24

Abstract: An SoC with a multiple level resource isolation system including initiator devices that conduct transactions with addressed slave devices via an interconnect, access identifier assignment (AIDA) devices that append an access identifier (AID) including a group identifier (GID) and a domain identifier (DID) to each transaction of a corresponding initiator device, access control (AC) devices that control access to slave devices based on an AID provided with a transaction, a partition manager that programs GIDs into the AIDA and AC devices for assigning slave devices to groups, and group managers that program DIDs into the AIDA devices for each matching GID programmed therein, and that program the AC devices with access rights to one or more DIDs for each slave device assigned to a corresponding group with a matching GID programmed therein.

公开(公告)号：US20240403126A1

公开(公告)日：2024-12-05

申请号：US18204251

申请日：2023-05-31

Applicant: XILINX, INC.

Inventor： Karthikeyan THANGAVEL ,  Anil Kumar MAMIDALA ,  Yashwant DAGAR ,  Mohammad Rafi SHAIK

IPC: G06F9/50 ,  G06F13/24

Abstract: A smart interrupt controller (SIC) routs an interrupt to a specific processor by dynamically changing the affinity of the interrupt based upon the processor power state and/or system load thereof. The SIC arbitrates interrupt servicing based on various parameters such as interrupt priority, interrupt affinity, processor load and processor power. Interrupt load sharing between selected processors increases overall computer system performance. Interrupt latency times decrease by avoiding unnecessary switching of processor power states from an inactive state to an active state by instead routing the interrupt to a different processor already in an active state. Interrupt latency times will decrease by routing the interrupt service request from a heavily loaded processor to one that is not so heavily loaded. Whereby active processor clock cycles are effectively utilized for interrupt servicing. Overall computer system power requirements will be reduced by eliminating unnecessary waking up of an inactive (sleeping) processor.

公开(公告)号：US20240370392A1

公开(公告)日：2024-11-07

申请号：US18667752

申请日：2024-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： HaiKun Dong ,  ZengRong Huang ,  Ling-Ling Wang ,  MinHua Wu ,  Jie Gao ,  RuiHong Liu

IPC: G06F13/24

Abstract: Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.

公开(公告)号：US12124401B2

公开(公告)日：2024-10-22

申请号：US18155499

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Francesco Gatta ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4295 ,  G06F13/24

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

公开(公告)号：US12111931B2

公开(公告)日：2024-10-08

申请号：US17853612

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Uri Weinrib ,  Barak Cherches ,  Clive David Bittlestone

IPC: G06F13/24 ,  G06F21/52 ,  G06F21/56

CPC classification number: G06F21/566 ,  G06F21/52 ,  G06F2221/034

Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

公开(公告)号：US12093706B2

公开(公告)日：2024-09-17

申请号：US18186748

申请日：2023-03-20

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

IPC: G06F9/455 ,  G06F13/10 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F9/455 ,  G06F13/105 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.