公开(公告)号：US12135658B2

公开(公告)日：2024-11-05

申请号：US17644130

申请日：2021-12-14

Applicant: Atmel Corporation

Inventor： Franck Lunadier ,  Vincent Debout

IPC: G06F13/16 ,  G06F13/14 ,  G06F13/36 ,  G06F13/364 ,  G06F13/42

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

公开(公告)号：US20240320039A1

公开(公告)日：2024-09-26

申请号：US18737728

申请日：2024-06-07

Applicant: Imagination Technologies Limited

Inventor： Jonas Olof Gunnar Källén

IPC: G06F9/48 ,  G06F9/50 ,  G06F13/16 ,  G06F13/18 ,  G06F13/20 ,  G06F13/28 ,  G06F13/364 ,  G06F16/901

CPC classification number: G06F9/4881 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4818 ,  G06F9/4831 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5027 ,  G06F9/5038 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/18 ,  G06F13/20 ,  G06F13/28 ,  G06F13/364 ,  G06F16/9027

Abstract: Methods and systems for generating common priority information for a plurality of requestors in a computing system that share a plurality of computing resources for use in a next cycle to arbitrate between the plurality of requestors, include generating, for each resource, priority information for the next cycle based on an arbitration scheme; generating, for each resource, relevant priority information for the next cycle based on the priority information for the next cycle for that resource, the relevant priority information for a resource being the priority information that relates to requestors that requested access to the resource in the current cycle and were not granted access to the resource in the current cycle; and combining the relevant priority information for the next cycle for each resource to generate the common priority information for the next cycle.

公开(公告)号：US20240037050A1

公开(公告)日：2024-02-01

申请号：US18279190

申请日：2022-02-28

Applicant: ETL SYSTEMS LIMITED

Inventor： Esen BAYAR ,  Sebastien Francis BUTSTRAEN ,  Simon Richard SWIFT

IPC: G06F13/364 ,  H04Q1/02

CPC classification number: G06F13/364 ,  H04Q1/136 ,  H04Q2201/04 ,  H04Q2201/10

Abstract: The application relates to modular electronic apparatus (1) for distribution of RF communication signals. The apparatus comprises a chassis (2) arranged to removably receive plural modules (3), at least some of which are arranged to receive and process RF communication signals. A communication path (17) is provided for modules to communicate with each other and/or with the chassis. Plural modules received in the chassis. When a module is received in the chassis, it is arranged to broadcast a message over the communication path indicating its presence in the chassis and its type. At least one other module is arranged to adapt its behaviour in response to the message.

公开(公告)号：US11835993B2

公开(公告)日：2023-12-05

申请号：US18179052

申请日：2023-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： DongSik Cho ,  Jeonghoon Kim ,  Rohitaswa Bhattacharya ,  Jaeshin Lee ,  Honggi Jeong

IPC: G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4004 ,  G06F13/364 ,  Y02D10/00

Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

公开(公告)号：US20230318606A1

公开(公告)日：2023-10-05

申请号：US17958554

申请日：2022-10-03

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ki Chul Noh

IPC: H03K19/173 ,  H03K19/17728 ,  G06F13/42 ,  G06F13/364

CPC classification number: H03K19/1737 ,  G06F13/364 ,  G06F13/4221 ,  H03K19/17728

Abstract: Provided herein may be an interface device and a method of operating the same. The interface device may include a first port configured to enable communication with a host, a second port configured to enable communication with the host, and a function manager including a plurality of variable functions that are selectively assignable to at least one of the first port and the second port.

公开(公告)号：US11726935B2

公开(公告)日：2023-08-15

申请号：US17315271

申请日：2021-05-08

Applicant: AyDeeKay LLC

Inventor： Scott David Kee

IPC: G06F3/00 ,  G06F13/26 ,  G06F13/40 ,  G06F3/06 ,  G06F12/06 ,  G06F12/0866 ,  G06F13/16 ,  G06F13/28 ,  G06F13/364 ,  G06F13/42 ,  G06F13/14 ,  G06F21/76

CPC classification number: G06F13/26 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0638 ,  G06F12/0866 ,  G06F13/14 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/364 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4282 ,  G06F21/76 ,  G06F2213/0062 ,  G06F2213/40 ,  G06F2221/2103

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

公开(公告)号：US20230251986A1

公开(公告)日：2023-08-10

申请号：US18296875

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Philip R. Lantz ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Saurabh Gayen

IPC: G06F13/364 ,  G06F13/24 ,  G06F9/50

CPC classification number: G06F13/364 ,  G06F9/5027 ,  G06F13/24

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

公开(公告)号：US11714647B2

公开(公告)日：2023-08-01

申请号：US17527288

申请日：2021-11-16

Applicant: Texas Instruments Incorporated

Inventor： Eric Robert Hansen ,  Krishnan Sridhar

IPC: G06F9/30 ,  G06F13/16 ,  G06F13/364 ,  G06F21/79 ,  G06F21/52

CPC classification number: G06F9/30105 ,  G06F13/1642 ,  G06F13/364 ,  G06F21/52 ,  G06F21/79 ,  G06F2212/206

Abstract: A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.

公开(公告)号：US11580044B2

公开(公告)日：2023-02-14

申请号：US17007814

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F13/00 ,  G06F13/364 ,  G06F30/3953

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.

公开(公告)号：US11567895B2

公开(公告)日：2023-01-31

申请号：US17337497

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/364 ,  G06F13/24

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.