公开(公告)号：US20240313135A1

公开(公告)日：2024-09-19

申请号：US18623868

申请日：2024-04-01

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/372

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/372 ,  G06F12/00 ,  G06F13/16 ,  Y02D10/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US20230244623A1

公开(公告)日：2023-08-03

申请号：US17545930

申请日：2021-12-08

Applicant: ATI Technologies ULC

Inventor： Michael E. McLean ,  Philip Ng

IPC: G06F13/372 ,  G06F13/364 ,  G06F13/366 ,  G06F13/40 ,  G06F9/48

CPC classification number: G06F13/372 ,  G06F9/4812 ,  G06F13/364 ,  G06F13/366 ,  G06F13/4059

Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window. This arbitration process continues for successive arbitration windows, oscillating between incrementing and decrementing the masking index value during the successive arbitration windows.

公开(公告)号：US11455265B2

公开(公告)日：2022-09-27

申请号：US17187427

申请日：2021-02-26

Applicant: Apple Inc.

Inventor： Roderick B. Hogan ,  Nathan A. Johanningsmeier ,  James B. Reedy

IPC: G06F13/37 ,  G06F13/372 ,  G06F1/20 ,  H04R3/00

Abstract: A group of transistors is configured to drive a bus at time slots, to express data on the bus. The group of transistors dissipates an amount of electrical energy when driving the bus to a logic level opposite to a logic level present on the bus in an immediate preceding time slot. The group of transistors is arranged to dump another amount of electrical energy. Dumping of the other amount of electrical energy is responsive to driving the bus to a logic level that is the same as present on the bus in an immediate preceding time slot. The dumped amount of electrical energy is equivalent to the amount of energy dissipated by the transistors when transitioning the bus to a different logic level. Other aspects are also described.

公开(公告)号：US20220214986A1

公开(公告)日：2022-07-07

申请号：US17605243

申请日：2020-03-02

Applicant: OMRON Corporation

Inventor： Toshinori TAMAI

IPC: G06F13/372 ,  G06F13/42 ,  G06F13/28 ,  G06F13/16

Abstract: Provided is a unit comprising a DMAC which, on the basis of a signal outputted from a time counting part which operates in synchronization with a time counting part of a PLC, does not communicate a memory via a serial bus in a control cycle of a CPU during at least a first period overlapping a period in which the CPU communicates with the memory, and communicates with the memory via the serial bus during a second period which begins after the first period.

公开(公告)号：US11256537B2

公开(公告)日：2022-02-22

申请号：US17117830

申请日：2020-12-10

Applicant: Mitsubishi Electric Corporation

Inventor： Jun Yabuki ,  Hitoshi Yamamoto ,  Ryo Okabe ,  Shinichi Ochiai ,  Hiroki Konaka

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F13/372

Abstract: An interrupt handler unit (130) generates a timer interrupt at an interrupt time, and executes an interrupt preparation process. A wait time period measurement unit (142) a measures a time period from completion of the interrupt preparation process to generation of a start request (201) as a wait time period. A time calculation unit (441) calculates a subtraction time period based on the wait time period measured by the wait time period measurement unit (142), and calculates a preparation time period that is the sum of a time period obtained by subtracting the subtraction time period from the wait time period and a processing time period of the interrupt preparation process. The time calculation unit (441) stores a time obtained by shifting back the preparation time period from the time of a next start request (201), as a next interrupt time, in a time storage unit (442).

公开(公告)号：US20210406207A1

公开(公告)日：2021-12-30

申请号：US16910194

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar NARALA

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/372 ,  G06F9/32

Abstract: Various embodiments include methods and systems performed by a processor of a first function block for providing secure timer synchronization with a second function block. Various embodiments may include storing, in a shared register space, a first time counter value in which the first time counter value is based on a global counter of the second function block, transmitting, from the shared register space, the stored first time counter value to a preload register of the first function block, receiving, by the first function block, a strobe signal from the second function block configured to enable the first time counter value in the preload register to be loaded into a global counter of the first function block, and configuring the global counter with the first time counter value from the preload register.

公开(公告)号：US11101393B2

公开(公告)日：2021-08-24

申请号：US16673431

申请日：2019-11-04

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F13/372 ,  G06F13/16 ,  G06F12/02 ,  G06F12/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US20210182226A1

公开(公告)日：2021-06-17

申请号：US17187427

申请日：2021-02-26

Applicant: Apple Inc.

Inventor： Roderick B. Hogan ,  Nathan A. Johanningsmeier ,  James B. Reedy

IPC: G06F13/372 ,  G06F1/20 ,  H04R3/00

Abstract: A group of transistors is configured to drive a bus at time slots, to express data on the bus. The group of transistors dissipates an amount of electrical energy when driving the bus to a logic level opposite to a logic level present on the bus in an immediate preceding time slot. The group of transistors is arranged to dump another amount of electrical energy. Dumping of the other amount of electrical energy is responsive to driving the bus to a logic level that is the same as present on the bus in an immediate preceding time slot. The dumped amount of electrical energy is equivalent to the amount of energy dissipated by the transistors when transitioning the bus to a different logic level. Other aspects are also described.

公开(公告)号：US10963410B2

公开(公告)日：2021-03-30

申请号：US15974635

申请日：2018-05-08

Applicant: Apple Inc.

Inventor： Roderick B. Hogan ,  Nathan A. Johanningsmeier ,  James B. Reedy

IPC: G06F13/37 ,  G06F13/372 ,  G06F1/20 ,  H04R3/00

Abstract: A group of transistors is configured to drive a bus at time slots, to express data on the bus. The group of transistors dissipates an amount of electrical energy when driving the bus to a logic level opposite to a logic level present on the bus in an immediate preceding time slot. The group of transistors is arranged to dump another amount of electrical energy. Dumping of the other amount of electrical energy is responsive to driving the bus to a logic level that is the same as present on the bus in an immediate preceding time slot. The dumped amount of electrical energy is equivalent to the amount of energy dissipated by the transistors when transitioning the bus to a different logic level. Other aspects are also described.

公开(公告)号：US20200133906A1

公开(公告)日：2020-04-30

申请号：US16663554

申请日：2019-10-25

Applicant: Siemens Aktiengesellschaft

Inventor： Sevan Haritounian

IPC: G06F13/372 ,  G06F13/42 ,  G06F13/16 ,  G06F11/30 ,  G06F11/22

Abstract: A peripheral module of a programmable controller and method for operating the peripheral module, wherein in a calibration mode a base voltage value is supplied by the peripheral module to a terminal via a switching device, the supply potential is changed at a start time by the peripheral module to the modified value and a response time at which the expected change occurs is acquired, and the valid time interval is ascertained by the peripheral module utilizing the start time and the response time.