公开(公告)号：US06725306B2

公开(公告)日：2004-04-20

申请号：US10083833

申请日：2002-02-27

申请人： Russell B. Stuber ,  Robert W. Moss ,  David O. Sluiter

发明人： Russell B. Stuber ,  Robert W. Moss ,  David O. Sluiter

IPC分类号： G06F1338

CPC分类号： G06F13/366

摘要： A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

摘要翻译： 从设备包括从主设备接收命令或数据以便先进先出地执行的队列。 状态寄存器响应队列提供STATUS_FULL信号，当队列充满命令时，STATUS_EMPTY信号在队列为空时。 配置寄存器提供标识从设备的维护状态的DEBUG信号。 响应于（1）STATUS_FULL信号或（2）DEBUG信号而不是STATUS_EMPTY信号来分配进一步的命令或停止数据总线，总线控制提供QUEUE_FULL信号。

公开(公告)号：US06629177B1

公开(公告)日：2003-09-30

申请号：US09472052

申请日：1999-12-27

申请人： Lai Hock Chong

发明人： Lai Hock Chong

IPC分类号： G06F1338

CPC分类号： G06F13/362 ,  G06F13/36 ,  G06F13/4031

摘要： Arbitration requests are received that belong to respective bus types. Each of the types is associated with a programmed value representing a potential number of times that requests of that type may win arbitration events that occur in a given time period. For at least some arbitration events that occur in the given time period, the invention updates a counter value for at least some of the types, the counter value for each of the types being set initially to the programmed value, and chooses a winning type in each of the arbitration events based on at least some of the counter values of the types of requests that are contending in the arbitration event.

摘要翻译： 收到属于相应总线类型的仲裁请求。 每个类型与编程的值相关联，该值表示该类型的请求可以赢得在给定时间段内发生的仲裁事件的潜在次数。 对于在给定时间段内发生的至少一些仲裁事件，本发明更新至少一些类型的计数器值，每个类型的计数器值最初被设置为编程值，并且选择获胜类型 基于在仲裁事件中竞争的请求类型的至少一些计数器值的每个仲裁事件。

公开(公告)号：US06611892B1

公开(公告)日：2003-08-26

申请号：US09578467

申请日：2000-05-26

申请人： Yuhi Sasaki ,  Toshiaki Shinohara ,  Kengo Tsuzuki

发明人： Yuhi Sasaki ,  Toshiaki Shinohara ,  Kengo Tsuzuki

IPC分类号： G06F1338

CPC分类号： H04L12/40058 ,  H04L12/40091 ,  H04L12/462

摘要： The two-way transmissions are performed between a first bus and a usual portal of a first full-duplex 3-portal bridge and between a second bus and a usual portal of a second full-duplex 3-portal bridge, respectively. The one-way transmission of an isochronous packet and an asynchronous stream packet is performed between transmission and reception portals of the first full-duplex 3-portal bridge and reception and transmission portals of the second full-duplex 3-portal bridge. The first full-duplex 3-portal bridge and the second full-duplex 3-portal bridge perform a conversion between the asynchronous stream packet and an asynchronous packet if necessary.

摘要翻译： 双向传输分别在第一全双工3入口网桥的第一总线和通常入口之间以及第二总线与第二全双工3端口桥的通常入口之间执行。 在第一全双工3端口桥接器的发送和接收端口以及第二全双工3端口桥接器的接收和发送端口之间执行同步分组和异步流分组的单向传输。 如果需要，第一个全双工3端口桥接器和第二个全双工3端口桥接器在异步流分组和异步分组之间执行转换。

公开(公告)号：US06570877B1

公开(公告)日：2003-05-27

申请号：US09287301

申请日：1999-04-07

申请人： Raymond J. Kloth ,  Kevin D. Morishige ,  Venkateshwar Rao Pullela

发明人： Raymond J. Kloth ,  Kevin D. Morishige ,  Venkateshwar Rao Pullela

IPC分类号： G06F1338

CPC分类号： H04L45/00 ,  H04L45/7453 ,  H04L49/90

摘要： A hardware search engine facility is provided to allow CPU search and update of a Forwarding Table CAM under the control of software running on the CPU. The hardware search engine provides one or more comparand-mask pairs which allow for a match, exclusion or magnitude comparison on specific entry values and/or the option to ignore or “don't care” certain bits of the entry. Control registers may be set in software to specify a start address and stop address in the CAM for the search. An indication of valid or invalid entries may be provided as well. Once the search is initiated by software, the search engine will read the entries sequentially starting from the programmed start address. It will perform a compare using the comparand-mask pair and attempt to identify a match. The locations in the CAM which match the search criteria may be put into a CPU-accessible memory. If the memory fills up before it can be read by the software, the search may be halted until the memory is emptied. A programmable action may instead, or in addition, be set to take place in the event of a match. Such programmable actions may include, but are not limited to, marking the entry, deleting the entry, change status bits corresponding to the entry, rewriting some of the entry, and the like.

摘要翻译： 提供硬件搜索引擎设备，以便在CPU上运行的软件控制下CPU搜索和更新转发表CAM。 硬件搜索引擎提供一个或多个比较屏蔽对，其允许对特定输入值进行匹配，排除或幅度比较和/或忽略或“不关心”条目的某些位的选项。 软件中可以设置控制寄存器，以指定搜索的CAM中的起始地址和停止地址。 也可以提供有效或无效的条目的指示。 一旦搜索由软件启动，搜索引擎将从编程的起始地址顺序读取条目。 它将使用比较掩码对执行比较，并尝试识别匹配。 符合搜索条件的CAM中的位置可以放入CPU可访问的存储器中。 如果在软件读取之前内存填满，则可能会停止搜索，直到内存清空为止。 可以替代地或另外设置可编程动作，以在匹配的情况下进行。 这样的可编程动作可以包括但不限于标记条目，删除条目，对应于条目的改变状态位，重写条目中的一些等等。

公开(公告)号：US06549948B1

公开(公告)日：2003-04-15

申请号：US08544153

申请日：1995-10-17

申请人： Akitomo Sasaki ,  Hiroaki Sato ,  Tomoaki Kawai ,  Hiroshi Okazaki ,  Takeshi Namikata

发明人： Akitomo Sasaki ,  Hiroaki Sato ,  Tomoaki Kawai ,  Hiroshi Okazaki ,  Takeshi Namikata

IPC分类号： G06F1338

CPC分类号： H04N7/152 ,  H04N21/42203 ,  H04N21/4223 ,  H04N21/440281 ,  H04N21/4424 ,  H04N21/4621

摘要： An information processing apparatus connected to a network to which plural information processing units are connected, in order to enable variation of the image frame rate in a specified information processing apparatus, thereby displaying a watched image in a smoother manner or decreasing the frame rate of unwatched images to increase the frame rate of another image. The information processing apparatus comprises a configuration for recognizing an instruction for varying the amount of image data released from an arbitrary one among the plural information processing apparatus and controlling the amount of image data released from the arbitrary information processing apparatus according to the recognition.

摘要翻译： 连接到连接有多个信息处理单元的网络的信息处理设备，以便能够在指定的信息处理设备中改变图像帧速率，从而以更平滑的方式显示观看的图像或降低未被捕获的帧速率 图像增加另一图像的帧速率。 信息处理装置包括用于识别用于改变从多个信息处理装置中的任意一个释放的图像数据的量的指令并根据识别来控制从任意信息处理装置释放的图像数据的量的配置。

公开(公告)号：US06535937B1

公开(公告)日：2003-03-18

申请号：US09503911

申请日：2000-02-15

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Russell Lee Ellison ,  Gregg Steven Lucas ,  Juan Antonio Yanes

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Russell Lee Ellison ,  Gregg Steven Lucas ,  Juan Antonio Yanes

IPC分类号： G06F1338

CPC分类号： G06F13/4221 ,  G06F13/4027

摘要： A method and system to verify the passage of one or more write commands sent from an originating location through a PCI bus system. An addressable data storage is located substantially at the end of the PCI bus system with respect to the originating location. A write command is sent by the originator subsequent to the one or more write commands, to a predetermined special end location address identifying the addressable storage. The command is accompanied by data comprising a predetermined special return address at the originating location. The PCI bus system transmits the write commands on a FIFO basis, so the one or more write commands precede the subsequently sent write command. Logic senses the subsequently sent write command, and responds to the command, sending a return echo write command to the predetermined special return address. The returning echo write command verifies the passage of the write commands and data through the PCI bus system. The predetermined special end location address is the key to identify the subsequently sent write command.

摘要翻译： 一种用于验证从始发位置通过PCI总线系统发送的一个或多个写入命令的通过的方法和系统。 相对于始发位置，可寻址数据存储器基本上位于PCI总线系统的末端。 写命令由发起者在一个或多个写入命令之后发送到标识可寻址存储器的预定特殊结束位置地址。 该命令伴随着在始发位置处包括预定的特殊返回地址的数据。 PCI总线系统以FIFO为基础发送写命令，因此一个或多个写命令先于随后发送的写命令。 逻辑检测随后发送的写入命令，并响应该命令，向预定的特殊返回地址发送返回回显写命令。 返回的回写写命令通过PCI总线系统验证写命令和数据的通过。 预定的特殊终端位置地址是识别随后发送的写命令的关键。

公开(公告)号：US06519630B1

公开(公告)日：2003-02-11

申请号：US09309172

申请日：1999-05-10

申请人： Takeshi Hanawa

发明人： Takeshi Hanawa

IPC分类号： G06F1338

CPC分类号： G06F17/214 ,  G06Q10/107

摘要： A method of transmitting and receiving an electronic mail includes the steps of: transmitting the electronic mail from a sender terminal to a receiver terminal, and receiving the electronic mail at the receiver terminal. The transmitting step includes the steps of producing the electronic mail including character codes of characters constituting a mail document, at least one conversion program for converting the characters to be displayed in a dynamic manner and an address of the receiver terminal, and transmitting the electronic mail. The receiving step includes: receiving the electronic mail; from a font storage unit storing character patterns corresponding to character codes, reading out the character patterns corresponding to the character codes included in the electronic mail; spreading the read-out character patterns on a bit map memory to produce bit map fonts; converting the bit map fonts by using the received conversion program according to the passage of time; and displaying the converted bit map fonts on a display device.

摘要翻译： 发送和接收电子邮件的方法包括以下步骤：将电子邮件从发送者终端发送到接收方终端，并在接收方终端接收电子邮件。 发送步骤包括以下步骤：产生包括构成邮件文件的字符的字符代码的电子邮件，至少一个转换程序，用于转换要以动态方式显示的字符和接收者终端的地址，以及发送电子邮件 。 接收步骤包括：接收电子邮件; 从存储对应于字符代码的字符模式的字体存储单元读出与包含在电子邮件中的字符代码相对应的字符模式; 将读出的字符图案扩展到位图存储器上以产生位图字体; 通过使用接收到的转换程序根据时间的流逝来转换位图字体; 以及在显示装置上显示转换后的位图字体。

公开(公告)号：US06467011B2

公开(公告)日：2002-10-15

申请号：US09859193

申请日：2001-05-15

申请人： Theodore G. Scardamalia ,  Lynn Parker West

发明人： Theodore G. Scardamalia ,  Lynn Parker West

IPC分类号： G06F1338

CPC分类号： G06F13/1663

摘要： A memory alias adapter, coupled to a processors memory bus, monitors processor memory accesses. Whenever a memory access corresponds to shared memory, rather than memory local to the processor, the adapter constructs a memory request message, and transmits the message over a network link to a shared memory unit. The shared memory unit performs the shared memory access and issues a response message over the network link. The memory alias adapter accepts the response message, and completes processor's memory access on the memory bus. As a result, it is transparent to the processor whether its memory access is to the local memory or to the shared memory,

摘要翻译： 耦合到处理器存储器总线的存储器别名适配器监视处理器存储器访问。 每当存储器访问对应于共享存储器而不是处理器本地存储器时，适配器构造存储器请求消息，并且通过网络链路将消息发送到共享存储器单元。 共享存储器单元执行共享存储器访问，并通过网络链路发出响应消息。 内存别名适配器接受响应消息，并在内存总线上完成处理器的内存访问。 因此，对于处理器来说，它的存储器访问是对本地存储器还是对共享存储器是透明的，

公开(公告)号：US06463483B1

公开(公告)日：2002-10-08

申请号：US09487846

申请日：2000-01-19

申请人： Steven Robert Imperiali

发明人： Steven Robert Imperiali

IPC分类号： G06F1338

CPC分类号： G06F13/28 ,  G06F13/4027

摘要： A computing or processing system including a microprocessor and a memory coupled together by a local bus, and also includes a north bridge providing translation to a PCI or other standard bus. The system also includes a device bus, which may or may not be coupled to the PCI bus by a south bridge. A device bus interface bypasses the north and south bridges, to provide a single-step interface to the device bus. This reduces the latency.

摘要翻译： 包括由本地总线耦合在一起的微处理器和存储器的计算或处理系统，还包括向PCI或其他标准总线提供转换的北桥。 该系统还包括设备总线，其可以或可以不被南桥耦合到PCI总线。 设备总线接口绕过北桥和南桥，为设备总线提供单步接口。 这减少了延迟。

公开(公告)号：US06442641B1

公开(公告)日：2002-08-27

申请号：US09327986

申请日：1999-06-08

申请人： James R Bury ,  Nick G Eskandari ,  Jeffrey J McCoskey

发明人： James R Bury ,  Nick G Eskandari ,  Jeffrey J McCoskey

IPC分类号： G06F1338

CPC分类号： G06F13/4027

摘要： An embodiment of the invention is directed at a method of processing multiple delayed write transactions, such as PCI transactions, by a bridge. The method involves receiving a number of requests for delayed write transactions on an initiating side of the bridge, and storing received transaction information for each of the requests in a separate one of a number of storage elements. An element containing newly received transaction information is marked valid if no received transaction information in other elements matches the newly received transaction information. Then, a delayed write transaction corresponding to the valid element is mastered on a target side of the bridge. If the corresponding delayed write transaction is completed on the target side, then the valid element is marked as complete. Thereafter, a new request received on the initiating side is signaled a successful termination if received transaction information for the new request matches that stored in the valid and complete element.

摘要翻译： 本发明的一个实施例涉及一种通过桥接处理多个延迟写入事务（诸如PCI事务）的方法。 该方法涉及在桥接的起始侧接收多个延迟写入事务的请求，并且将接收到的每个请求的事务信息存储在多个存储元件中的单独的一个中。 如果其他元素中没有接收到的交易信息与新接收到的交易信息匹配，则包含新接收的交易信息的元素被标记为有效。 然后，将与有效元素相对应的延迟写入事务掌握在网桥的目标侧上。 如果相应的延迟写事务在目标端完成，则有效元素被标记为完成。 此后，如果新请求的接收到的交易信息与存储在有效和完整元素中的交易信息相匹配，则在发起端接收到的新请求被发信号通知成功终止。