公开(公告)号：US12087348B2

公开(公告)日：2024-09-10

申请号：US17766326

申请日：2020-11-06

申请人： TOBB EKONOMI VE TEKNOLOJI UNIVERSITESI

发明人： Fahrettin Koc ,  Oguz Ergin

IPC分类号： G11C11/24 ,  G11C11/4074

CPC分类号： G11C11/4074

摘要： Disclosed is an adaptive application of bias voltages to the access transistors in the cells in dynamic random access memory (DRAM) structures, according to the access pattern of the rows, in other words, whether the rows are accessed and/or how often rows are accessed.

公开(公告)号：US12050536B2

公开(公告)日：2024-07-30

申请号：US18117974

申请日：2023-03-06

申请人： Lodestar Licensing Group LLC

发明人： Richard C. Murphy

IPC分类号： G11C11/24 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0895 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G11C19/00

CPC分类号： G06F12/0864 ,  G06F9/30036 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0895 ,  G11C7/1006 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/1012 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/6032 ,  G11C11/4094 ,  G11C19/00

摘要： The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

公开(公告)号：US12040042B2

公开(公告)日：2024-07-16

申请号：US18101140

申请日：2023-01-25

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Jun Koyama ,  Shunpei Yamazaki

IPC分类号： G11C11/24 ,  G11C5/10 ,  G11C7/12 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC分类号： G11C5/10 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/7869 ,  H10B12/05 ,  H10B12/30 ,  H10B12/50 ,  H01L27/1225 ,  H10B12/482

摘要： An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.

公开(公告)号：US12002535B2

公开(公告)日：2024-06-04

申请号：US17640452

申请日：2020-09-08

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Takeshi Aoki ,  Munehiro Kozuma ,  Masashi Fujita ,  Takahiko Ishizu

IPC分类号： G11C11/24 ,  G11C7/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/54

CPC分类号： G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/54

摘要： A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.

公开(公告)号：US11922988B2

公开(公告)日：2024-03-05

申请号：US17674301

申请日：2022-02-17

申请人： Korea Advanced Institute of Science and Technology

发明人： Yang-Kyu Choi ,  Myung-Su Kim

IPC分类号： G11C11/24 ,  G11C11/404 ,  G11C11/4096

CPC分类号： G11C11/404 ,  G11C11/4096

摘要： Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.

公开(公告)号：US11830539B2

公开(公告)日：2023-11-28

申请号：US17935121

申请日：2022-09-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Junsoo Kim ,  Minwoo Kwon

IPC分类号： G11C11/24 ,  G11C11/408 ,  H10B12/00

CPC分类号： G11C11/4085 ,  H10B12/30 ,  H10B12/50

摘要： An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.

公开(公告)号：US11778808B2

公开(公告)日：2023-10-03

申请号：US17472902

申请日：2021-09-13

申请人： Kioxia Corporation

发明人： Teruhisa Sonohara ,  Shunichi Seno ,  Hiroki Tokuhira ,  Fumitaka Arai

IPC分类号： G11C11/24 ,  H10B12/00 ,  H01L29/786 ,  G11C11/4076 ,  H01L29/66 ,  G11C11/406 ,  G11C11/4096 ,  H01L21/02

CPC分类号： H10B12/30 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40615 ,  H01L21/02565 ,  H01L29/66969 ,  H01L29/7869 ,  H10B12/03 ,  H10B12/05

摘要： A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

公开(公告)号：US11751409B2

公开(公告)日：2023-09-05

申请号：US17466442

申请日：2021-09-03

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC分类号： H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

摘要： To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-lth sub memory cell.

公开(公告)号：US11737283B1

公开(公告)日：2023-08-22

申请号：US17516594

申请日：2021-11-01

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/00 ,  H10B53/30 ,  G11C11/24

CPC分类号： H10B53/30 ,  G11C11/24

摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

公开(公告)号：US20220352167A1

公开(公告)日：2022-11-03

申请号：US17867544

申请日：2022-07-18

申请人： Micron Technology, Inc.

发明人： Durai Vishak Nirmal Ramaswamy

IPC分类号： H01L27/105 ,  G11C11/24 ,  G11C11/22 ,  H01L27/108 ,  H01L27/06

摘要： A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.