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2935 条记录 (耗时 0.034 秒)

    Memory device
    1.
    发明授权
    Memory device 有权

    公开(公告)号：US12125522B2

    公开(公告)日：2024-10-22

    申请号：US17955978

    申请日：2022-09-29

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kyeong Tae Nam ,  Young Hun Seo ,  Mi Ji Jang

    IPC分类号： G11C11/40 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

    CPC分类号： G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

    摘要： A memory device is provided. The memory device comprises a memory cell array connected to a first bit line and a complementary bit line, a first bit line sense amplifier configured to sense, amplify and the first bit line signal output a first bit line signal and the complimentary bit signal output on a complementary bit line signal output on the first bit line and the complementary bit line, a charge transfer transistor connected to the first bit line sense amplifier and configured to be gated by a charge transfer signal of a first node, an offset transistor configured to connect the first node and a second node based on an offset removal signal and a pre-charging transistor connected between the second node and a pre-charging voltage line and the pre-charging transistor being configured to pre-charge the first bit line or the complementary bit line based on an equalizing signal.

    Memory device through use of semiconductor device
    2.
    发明授权
    Memory device through use of semiconductor device 有权

    公开(公告)号：US12108589B2

    公开(公告)日：2024-10-01

    申请号：US17741914

    申请日：2022-05-11

    申请人： Unisantis Electronics Singapore Pte. Ltd.

    发明人： Koji Sakui ,  Nozomu Harada

    IPC分类号： G11C11/40 ,  G11C11/404 ,  G11C11/4096 ,  H10B12/00

    CPC分类号： H10B12/20 ,  G11C11/404 ,  G11C11/4096

    摘要： A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form. The memory device controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the pages to perform a page write operation of holding a hole group formed by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of each of the memory cells is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line. The bit line is connected to a sense amplifier circuit via a switching circuit. When in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the sense amplifier circuit.

    Semiconductor device having read data buses and write data buses
    5.
    发明授权
    Semiconductor device having read data buses and write data buses 有权

    公开(公告)号：US12094522B2

    公开(公告)日：2024-09-17

    申请号：US17936785

    申请日：2022-09-29

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Akeno Ito ,  Mamoru Nishizaki

    IPC分类号： G11C11/40 ,  G11C11/4091 ,  G11C11/4096

    CPC分类号： G11C11/4091 ,  G11C11/4096

    摘要： An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.

    Memory device
    6.
    发明授权
    Memory device 有权

    公开(公告)号：US12094518B2

    公开(公告)日：2024-09-17

    申请号：US17988760

    申请日：2022-11-17

    申请人： MACRONIX International Co., Ltd.

    发明人： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

    IPC分类号： G11C11/40 ,  G11C11/4074 ,  G11C11/408

    CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4087

    摘要： A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.

    Memory device
    7.
    发明授权
    Memory device 有权

    公开(公告)号：US12087346B2

    公开(公告)日：2024-09-10

    申请号：US17750775

    申请日：2022-05-23

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seung Ki Hong ,  Seung Jun Lee

    IPC分类号： G11C11/40 ,  G11C11/406 ,  G11C11/4093

    CPC分类号： G11C11/40618 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4093

    摘要： A memory device includes a memory cell array, a row select circuit, a refresh controller and a memory control logic. The memory cell array includes memory cells arranged in rows and columns. The row select circuit is connected to the rows. The refresh controller controls the row select circuit to apply a refresh operating voltage to one or more rows. The memory control logic decodes a command received from a memory controller and outputs a refresh command and external refresh address information. The refresh controller controls the row select circuit to perform one of an external refresh operation and an internal refresh operation, based on the refresh command that is output from the memory controller and based on whether a first row-hammering row address of the internal refresh operation is identical with a second row-hammering row address of the external refresh operation.

    Memory system, control method, and power control circuit
    8.
    发明授权
    Memory system, control method, and power control circuit 有权

    公开(公告)号：US12027196B2

    公开(公告)日：2024-07-02

    申请号：US17856909

    申请日：2022-07-01

    申请人： KIOXIA CORPORATION

    发明人： Megumi Shibatani ,  Takashi Ooshima ,  Nobuyuki Suzuki

    IPC分类号： G11C11/40 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4096

    CPC分类号： G11C11/4074 ,  G11C11/4072 ,  G11C11/4096

    摘要： A memory system includes: a first nonvolatile memory; a second volatile memory; a controller; a power control circuit configured to perform control such that a first voltage is applied to the first memory, the second memory, and the controller based on first power supplied from an external power supply; and a power storage device configured to supply second power to the power control circuit while the first power from the external power supply is interrupted. While the first power supplied from outside is interrupted, the power control circuit applies a second voltage based on the second power supplied from the power storage device to the first memory, the second memory, and the controller. The power control circuit stops the application of the second voltage to the second memory after the data is read from the second memory and before the data is written into the first memory.