公开(公告)号：US20240355378A1

公开(公告)日：2024-10-24

申请号：US18758749

申请日：2024-06-28

申请人： MICRON TECHNOLOGY, INC.

发明人： Akira Yamashita ,  Kenji Asaki

IPC分类号： G11C11/4093 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC分类号： G11C11/4093 ,  G11C11/4076 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

公开(公告)号：US20240347098A1

公开(公告)日：2024-10-17

申请号：US18624920

申请日：2024-04-02

申请人： Micron Technology, Inc.

发明人： Yang Lu

IPC分类号： G11C11/406 ,  G11C11/4093

CPC分类号： G11C11/40618 ,  G11C11/40615 ,  G11C11/4093

摘要： Apparatuses and techniques for implementing usage-based disturbance mitigation are described. In some examples, a Total Mitigation Pump Pair (TMPP) queue and a dynamic Mitigation Threshold (MT) can improve the mitigation efficiency of usage-based disturbances while reducing power requirements and increasing performance impact. In various aspects, the TMPP queue is a first-in first out (FIFO) queue useful to implement the described disturbance mitigation techniques.

公开(公告)号：US20240331761A1

公开(公告)日：2024-10-03

申请号：US18126680

申请日：2023-03-27

申请人： Intel Corporation

发明人： Charles Augustine ,  Amlan Ghosh ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah ,  Feroze Merchant

IPC分类号： G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

CPC分类号： G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

摘要： An apparatus includes a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, and a second PMOS transistor including a source coupled to an output of the first inverter. The first PMOS transistor and the second PMOS transistor are disposed in at least one PMOS layer configured between a first metal layer and a second metal layer. The register file circuit further includes a first via connecting a gate of the first PMOS transistor and a gate of the second PMOS transistor in the at least one PMOS layer to the first metal layer.

公开(公告)号：US12106798B2

公开(公告)日：2024-10-01

申请号：US18358049

申请日：2023-07-25

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chi-Sing Lo

IPC分类号： G11C11/4093

CPC分类号： G11C11/4093

摘要： A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. The pre-stage amplifier circuits are configured to receive an input signal and a reference voltage signal, output first pre-stage amplifying signals through a first connection node and a second connection node separately, and output second pre-stage amplifying signals through a third connection node and a fourth connection node separately. The post-stage amplifier circuit is configured to receive the first pre-stage amplifying signals and the second pre-stage amplifying signals from the pair of pre-stage amplifier circuits through the first connection node, the second connection node, the third connection node and the fourth connection node separately, and output a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals.

公开(公告)号：US12106797B2

公开(公告)日：2024-10-01

申请号：US17859153

申请日：2022-07-07

申请人： INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

发明人： Seong Ook Jung ,  In Jun Jung ,  Tae Hyun Kim

IPC分类号： G11C11/34 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4094 ,  H03K19/017

CPC分类号： G11C11/4093 ,  G11C11/4085 ,  G11C11/4094 ,  H03K19/01742

摘要： A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.

公开(公告)号：US20240321340A1

公开(公告)日：2024-09-26

申请号：US18588686

申请日：2024-02-27

申请人： Micron Technology, Inc.

发明人： Martin Brox ,  Milena Tsvetkova Ivanov ,  Natalija Jovanovic

IPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C11/4093

CPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C11/4093

摘要： Methods, systems, and devices for techniques and devices to reduce bus cross talk are described. Adjacent conductive lines in a bus of a memory system may be electrically coupled if both conductive lines are concurrently driven to a high-state. For example, the bus may include a logic circuit coupled between the adjacent conductive lines, which may selectively couple the conductive lines based on the voltage applied to each conductive line. In some examples, the logic circuit may include an input coupled to the control signals of the drivers associated with the adjacent conductive lines. If both control signals are concurrently high, the logic circuit may activate a transistor to couple the conductive lines. Such electrical coupling may reduce or eliminate the capacitive coupling between the two conductive lines when both are driven to a high state, which may result in increased reliability of signals in the conductive lines.

公开(公告)号：US12094525B2

公开(公告)日：2024-09-17

申请号：US17814254

申请日：2022-07-22

申请人： International Business Machines Corporation

发明人： Ravi Nair ,  Swagath Venkataramani ,  Vijayalakshmi Srinivasan ,  Arvind Kumar

IPC分类号： G11C11/4096 ,  G11C5/06 ,  G11C11/4093

CPC分类号： G11C11/4096 ,  G11C5/06 ,  G11C11/4093

摘要： A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

公开(公告)号：US12073910B2

公开(公告)日：2024-08-27

申请号：US18169769

申请日：2023-02-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

IPC分类号： G11C7/10 ,  G06F3/06 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C11/408

CPC分类号： G11C7/1012 ,  G06F3/0619 ,  G11C11/4093 ,  G11C11/4096 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/4082 ,  G11C2207/005

摘要： A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

公开(公告)号：US20240274183A1

公开(公告)日：2024-08-15

申请号：US18582185

申请日：2024-02-20

申请人： Micron Technology, Inc.

发明人： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC分类号： G11C11/408 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093

CPC分类号： G11C11/4082 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093

摘要： Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US20240274181A1

公开(公告)日：2024-08-15

申请号：US18584669

申请日：2024-02-22

申请人： Rambus Inc.

发明人： Steven C. WOO ,  Taeksang SONG

IPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/4093

CPC分类号： G11C11/40618 ,  G11C11/408 ,  G11C11/4093

摘要： The internal row addressing of each DRAM on a module is mapped such that row hammer affects different neighboring row addresses in each DRAM. Because the external row address to internal row address mapping scheme ensures that each set of neighboring rows for a given externally addressed row is different for each DRAM on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each DRAM. This has the effect of confining the row hammer errors for each row that is hammered to a single DRAM per externally addressed neighboring row. By confining the row hammer errors to a single DRAM, the row hammer errors are correctible using a single device data correct (SDDC) scheme.