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    Memory device using semiconductor elements
    2.
    发明授权
    Memory device using semiconductor elements 有权

    公开(公告)号：US12101925B2

    公开(公告)日：2024-09-24

    申请号：US17739849

    申请日：2022-05-09

    申请人： Unisantis Electronics Singapore Pte. Ltd.

    发明人： Nozomu Harada ,  Koji Sakui

    IPC分类号： H10B12/00 ,  G11C11/4097

    CPC分类号： H10B12/20 ,  G11C11/4097

    摘要： Provided on a substrate are an N+ layer connecting to a source line SL and an N+ layer connecting to a bit line BL that are located at opposite ends of a Si pillar standing in an upright position along the vertical direction, an N layer continuous with the N+ layer, an N layer continuous with the N+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connecting to a plate line PL, and a second gate conductor layer surrounding a second gate insulating layer surrounding the Si pillar and connecting to a word line WL. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data retention operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region of the Si pillar, and a data erase operation for removing the holes from the channel region.

    Local amplifying circuit, data readout method and memory
    4.
    发明授权
    Local amplifying circuit, data readout method and memory 有权

    公开(公告)号：US12080337B2

    公开(公告)日：2024-09-03

    申请号：US17854153

    申请日：2022-06-30

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Ying Wang

    IPC分类号： G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

    摘要： A local amplifying circuit, a data readout method and a memory are provided. The local amplifying circuit includes: write control transistors, configured to connect a global data line to a local data line based on a write enable signal; column selection transistors, configured to connect a bit line to the local data line based on a column selection signal; a first control NMOS transistor, having a gate connected to the local data line, one of a source and a drain being connected to the global data line and the other being connected to a corresponding read control transistor; a second control NMOS transistor, having a gate connected to a complementary local data line, one of a source and a drain being connected to a complementary global data line and the other being connected to a corresponding read control transistor.

    MEMORY ARRAY FOR COMPUTE-IN-MEMORY AND THE OPERATING METHOD THEREOF
    6.
    发明公开
    MEMORY ARRAY FOR COMPUTE-IN-MEMORY AND THE OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240153552A1

    公开(公告)日：2024-05-09

    申请号：US18175895

    申请日：2023-02-28

    申请人： NATIONAL YANG MING CHIAO TUNG UNIVERSITY

    发明人： Tian-Sheuan Chang ,  Wei-Zen Chen ,  Shyh-Jye Jou ,  Shu-Hung Kuo ,  Shih-Hang Kao ,  Li-Kai Chen

    IPC分类号： G11C11/54 ,  G11C11/408 ,  G11C11/4097

    CPC分类号： G11C11/54 ,  G11C11/4085 ,  G11C11/4097

    摘要： A memory array for computing-in-memory (CIM) is disclosed. The memory array for CIM includes a bit cell array, at least one word line and at least one bit line. The bit cell array has a plurality of bit cells, wherein each bit cell is operated at an operating voltage. The at least one word line is electrically connected to the bit cell array, wherein the at least one word line is associated with a first parameter. The at least one bit line is electrically connected to the bit cell array, wherein the bit cells extend along a specific direction, each the at least one bit line has an electrical parameter associated therewith, each the bit cell is associated with a second parameter, a first quantity of the plurality of bit cells of the bit cell array extends along the specific direction, and the memory array determines how an expansion associated with at least one of the first parameter and the second parameter is according to the specific direction.

    SEMICONDUCTOR DEVICE
    9.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240038285A1

    公开(公告)日：2024-02-01

    申请号：US18064757

    申请日：2022-12-12

    申请人： SK hynix Inc.

    发明人： Take Kyun WOO

    IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C5/06 ,  H01L27/105

    CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C11/4097 ,  G11C5/063 ,  H01L27/105

    摘要： A semiconductor device may include: a first substrate structure including: a first substrate; a first word line, a first bit line, a second bit line, a second word line, a third word line, a third bit line, a fourth bit line, and a fourth word line that are sequentially arranged over the first substrate in a vertical direction; and first, second, third, and fourth memory cells, the first memory cell being disposed between the first word line and the first bit line, the second memory cell being disposed between the second word line and the second bit line, the third memory cell being disposed between the third word line and the third bit line, and the fourth memory cell being disposed between the fourth word line and the fourth bit line; and a second substrate structure disposed over the first substrate structure and including a second substrate.