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    Read and programming decoding system for analog neural memory
    1.
    发明授权
    Read and programming decoding system for analog neural memory 有权

    公开(公告)号：US12237011B2

    公开(公告)日：2025-02-25

    申请号：US17853315

    申请日：2022-06-29

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

    IPC: G11C11/56 ,  G06F17/16 ,  G06N3/06 ,  G11C11/16 ,  G11C11/4074

    Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

    MEMORY DEVICE AND READ OPERATION DURING SUSPENSION OF PROGRAM OPERATION THEREOF
    2.
    发明申请
    MEMORY DEVICE AND READ OPERATION DURING SUSPENSION OF PROGRAM OPERATION THEREOF 有权

    公开(公告)号：US20250061949A1

    公开(公告)日：2025-02-20

    申请号：US18930430

    申请日：2024-10-29

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Lei Shi ,  Zhuqin Duan ,  Jialiang Deng

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24

    Abstract: A memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. The array of memory cells includes a first memory cell and a second memory cell. Each of the first and second memory cells is configured to store N-bits data. The peripheral circuit includes a page buffer circuit and control logic. The page buffer circuit includes at least a page buffer circuit coupled to the first and second memory cells, respectively. The page buffer circuit includes a sense out (SO) node and a cache storage unit. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell, control the page buffer circuit to store suspended program information associated with a suspension of the program operation, and perform the read operation on the second memory cell, including directly storing one of N-bits data of the second memory cell into the cache storage unit through the SO node.

    Memory device, memory system, and method of operating the same
    3.
    发明授权
    Memory device, memory system, and method of operating the same 有权

    公开(公告)号：US12224004B2

    公开(公告)日：2025-02-11

    申请号：US18081065

    申请日：2022-12-14

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Weijun Wan ,  Yue Sheng

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

    Abstract: A peripheral circuit of a memory device includes page buffers. Each page buffer includes a main latch, a bias latch, (N−1) data latches, and a cache latch coupled to a data path. The peripheral circuit is further configured to: in the process of programming a first physical page, disable a bit line bias function to release the bias latch to replace one of N page latches to perform a programming verification of memory states; release one of the N page latches to cache program data of one of the N logical pages of a second physical page; and in the process of programming the first physical page, store the program data of the one of the N logical pages of the second physical page in a released page latch.

    Non-volatile memory device and programming method thereof
    4.
    发明授权
    Non-volatile memory device and programming method thereof 有权

    公开(公告)号：US12217807B2

    公开(公告)日：2025-02-04

    申请号：US17960346

    申请日：2022-10-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonghyuk Choi ,  Yohan Lee

    IPC: G11C7/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

    Abstract: An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, the operating method include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings.

    Programming techniques to reduce programming stress in a memory device
    6.
    发明授权
    Programming techniques to reduce programming stress in a memory device 有权

    公开(公告)号：US12205647B2

    公开(公告)日：2025-01-21

    申请号：US17713458

    申请日：2022-04-05

    Applicant: SanDisk Technologies LLC

    Inventor： Xiaoyu Che ,  Yanjie Wang ,  Guirong Liang

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27 ,  H10B43/27

    Abstract: The memory device includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is provided, and the controller is configured to program the memory cells to respective threshold voltages in a programming operation. The controller is configured to, in the programming operation, apply a first voltage to a control gate of a selected word line of the plurality of word lines. The controller is also configured to continuously ramp a voltage applied to the control gate of the selected word line from the first voltage to a programming voltage over a first duration. The controller is further configured to hold the voltage applied to the control gate of the selected word line at the programming voltage over a second duration that is less than the first duration.

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