公开(公告)号：US06831852B2

公开(公告)日：2004-12-14

申请号：US10442439

申请日：2003-05-22

申请人： Yoshiyuki Ishigaki ,  Tsuyoshi Koga ,  Yasuhiro Fujii

发明人： Yoshiyuki Ishigaki ,  Tsuyoshi Koga ,  Yasuhiro Fujii

IPC分类号： G11C1124

CPC分类号： G11C11/412 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T6. At least a portion of the latch circuit is formed above the bit line.

摘要翻译： 半导体器件包括：电容器：具有杂质区域的存取晶体管，控制存储在电容器中的电荷的输入/输出，其中一个杂质区域电连接到电容器; 位于硅衬底上方的锁存电路，并存储电容器的存储节点的电位; 以及连接到存取晶体管T6的另一个杂质区的位线。 锁存电路的至少一部分形成在位线上方。

公开(公告)号：US06762951B2

公开(公告)日：2004-07-13

申请号：US10330077

申请日：2002-12-30

申请人： Kiyoo Itoh ,  Kazuo Nakazato

发明人： Kiyoo Itoh ,  Kazuo Nakazato

IPC分类号： G11C1124

CPC分类号： G11C11/4076 ,  G11C11/404 ,  G11C11/405 ,  G11C16/0408 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.

摘要翻译： 一种半导体集成电路器件，其利用包含晶体管来写入信息的存储单元和存储MOSFET来保持栅极中的信息电压，放置为与写入数据线和读取数据线相交的字线，用于连接到控制器 写入晶体管的端子和用于响应于来自所述写入晶体管的选择信号而从所述存储单元发出对应于读取信号的所述读取数据线上的输出的存储单元阵列，并且借助于数据选择电路，从 所述多条读取数据线从数据线选择电路连接到第一或第二公共数据线，在第一周期内将所述读取数据线预充电到第一电压，借助于 所述存储器单元的第二存储MOSFET设置为在所述第二周期内选择的所述字线的状态，将所述第一和第二公共数据线预充电到第三伏特 在所述第一周期内的所述第一和所述第二电压之间，并且在所述第二周期内通过使用所述另一个上的预充电电压来放大在所述第二周期内由所述数据线选择电路选择的读数据线上出现在任一公共数据线上的读信号 公共数据线作为参考电压。

公开(公告)号：US06714436B1

公开(公告)日：2004-03-30

申请号：US10393053

申请日：2003-03-20

申请人： James D. Burnett ,  Alexander Hoefler

发明人： James D. Burnett ,  Alexander Hoefler

IPC分类号： G11C1124

CPC分类号： H01L27/10844 ,  G11C11/40 ,  G11C11/404 ,  H01L27/108 ,  H01L29/7841

摘要： A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region (12). Data is written to the cell by the instigation of band-to-band tunneling (BTBT) and the resulting generation of hole/electron pairs. Electrons are drawn from the body region through forward-biased drain (14) and source (15) regions so that holes accumulate in the body region. The increase in threshold voltage, caused by the accumulation of holes, may be defined and detected as a logic level (ONE, for example). In one embodiment, a split biasing scheme applies substantially identical voltages to the drain and to the source and a negative bias to the gate. In alternative embodiments, a negative gate bias is not required and the drain and source bias voltages may be offset so as to mitigate source damage.

摘要翻译： 一种用于将数据写入单晶体管无电容（1T / 0C）RAM单元的方法，其中单元结构以具有浮体区域（12）的SOI MOS晶体管为前提。 通过带通隧道（BTBT）的引发和所产生的空穴/电子对来将数据写入单元。 电子通过正向偏置的漏极（14）和源极（15）区域从体区域被拉出，使得孔体积在体区中。 可以定义并检测由空穴累积引起的阈值电压的增加，作为逻辑电平（例如，一个）。 在一个实施例中，分离偏置方案将基本相同的电压施加到漏极和源极以及向栅极施加负偏压。 在替代实施例中，不需要负栅极偏置，并且可以抵消漏极和源极偏置电压以便减轻源损伤。

公开(公告)号：US06707705B2

公开(公告)日：2004-03-16

申请号：US10113413

申请日：2002-04-01

申请人： Paul Schmölz ,  Jean-Marc Dortu ,  Robert Feurle ,  Andreas Täuber

发明人： Paul Schmölz ,  Jean-Marc Dortu ,  Robert Feurle ,  Andreas Täuber

IPC分类号： G11C1124

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4085

摘要： In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

摘要翻译： 为了操作具有存储单元阵列的集成动态存储器，该存储单元阵列具有位线和字线，用于执行存储器访问的多个单独动作 - 从一行字线的激活直到字线预充电 以时钟信号的同步方式进行控制。 在开始时，编写一个用于定义至少两个单独动作之间定义数量的时钟周期的值。 为此，控制电路具有可编程单元。 以这种方式，结合时钟电路，即使在可变时钟频率下也可以实现相对较高的数据吞吐量。

公开(公告)号：US06665207B2

公开(公告)日：2003-12-16

申请号：US09992203

申请日：2001-11-14

申请人： Phillip G. Wald ,  Casey Kurth ,  Scott Derner

发明人： Phillip G. Wald ,  Casey Kurth ,  Scott Derner

IPC分类号： G11C1124

CPC分类号： H01L27/10894 ,  G11C17/12 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852 ,  H01L27/112 ,  H01L27/11213 ,  H01L28/84

摘要： A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed and a conductor is fabricated in contact with the DRAM storage plate. The memory allows ROM cells to be hard programmed to different data states, such as Vcc and Vss.

公开(公告)号：US06661702B1

公开(公告)日：2003-12-09

申请号：US10350653

申请日：2003-01-24

申请人： Darryl Gene Walker

发明人： Darryl Gene Walker

IPC分类号： G11C1124

CPC分类号： H01L27/10873 ,  G11C11/404 ,  G11C11/4085 ,  H01L27/10808 ,  Y10S257/907 ,  Y10S257/908

摘要： A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel region (324). A top gate (318) is disposed over the channel region (324) and a bottom gate (310) is disposed below the channel region (324). The top gate (318) and bottom gate (310) are commonly driven to provide greater control of the pass transistor (302) operation, including an off state with reduced source-to-drain leakage. The DRAM array (400) includes memory cells (414) having pass transistors (500) with double-gate structures. Memory cells (414) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (600). The DRAM array (400) further includes a strapping area that is void of memory cells. Conductive contact between the top word line bottom word line, and word line strap layer (600) of each row is made within the strapping area by way of strapping vias (604) and top-to-bottom word line vias (602).

摘要翻译： 公开了一种动态随机存取存储器（DRAM）单元和相关阵列。 DRAM单元（300）包括存储电容器（304）和通过晶体管（302）。 传输晶体管（302）包括源极区（322），漏极区（320）和沟道区（324）。 顶部栅极（318）设置在沟道区域（324）上方，底部栅极（310）设置在沟道区域（324）的下方。 通常驱动顶栅（318）和底栅（310）以提供对传输晶体管（302）操作的更大控制，包括具有减少的源漏漏泄漏的关断状态。 DRAM阵列（400）包括具有双栅结构的传输晶体管（500）的存储单元（414）。 同一行内的存储单元（414）通常耦合到顶部字线和底部字线。 顶部和底部字线的电阻通过字线带层（600）减小。 DRAM阵列（400）还包括无存储单元的捆扎区域。 通过捆扎通孔（604）和顶部到底部字线通孔（602），在捆扎区域内在每个行的顶部字线底部字线和字线条带（600）之间形成导电接触。

公开(公告)号：US06501675B2

公开(公告)日：2002-12-31

申请号：US09854987

申请日：2001-05-14

申请人： Harold Pilo ,  Robert E. Busch

发明人： Harold Pilo ,  Robert E. Busch

IPC分类号： G11C1124

CPC分类号： G11C8/14 ,  G11C7/14 ,  G11C11/4099

摘要： A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time. The write-back of the reference cells can be hidden since an alternate cell is available for next cycle's reference bitline generation.

摘要翻译： 快速DRAM存储器使用地面感测，而不是传统的Vdd / 2感测。 所选择的DRAM单元连接到位线真（BLT）或位线补码（BLC）。 在每个循环开始时，BLT和BLC恢复到地电位。 为每个位线提供一对交替参考单元。 当所选择的DRAM单元连接到BLT或BLC时，该对中的第一参考单元连接到另一位线，以向可与所选择的DRAM单元提供的电压进行比较的另一位线提供参考电压。 在使用相同位线的后续周期中，使用该对中的第二参考单元。 因此，在开始下一个周期之前，不需要等待第一个参考单元进行充电。 该对中的第一和第二参考单元之间的切换以这种方式交替地产生更快的周期时间。 可以隐藏参考单元的回写，因为替代单元可用于下一循环的参考位线生成。

公开(公告)号：US06493252B1

公开(公告)日：2002-12-10

申请号：US09930522

申请日：2001-08-15

申请人： Jeff A. McClain

发明人： Jeff A. McClain

IPC分类号： G11C1124

CPC分类号： H01L27/10882 ,  G11C11/4045 ,  H01L27/10805 ,  H01L27/10897

摘要： Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.

公开(公告)号：US06452832B2

公开(公告)日：2002-09-17

申请号：US09681200

申请日：2001-02-19

申请人： Kohji Hosokawa

发明人： Kohji Hosokawa

IPC分类号： G11C1124

CPC分类号： G11C7/1006 ,  G11C7/1048

摘要： To provide a DRAM circuit capable of achieving a high speed write operation even when the write operation is accompanied with a write masking operation, and a method of controlling the same. A DRAM circuit of the present invention has a novel column switch for connecting a bit line pair and a data line pair via a sense amplifier. The novel column switch has a function to separate a bit line pair corresponding to a selected data line pair during the write mask operation. As a result, even if the column switch is made to be ON before the it line pair is sufficiently amplified by the sense amplifier, there is no fear that data on the bit line pair is destroyed due to a malfunction of the sense amplifier, thus making it possible to achieve a high speed write operation without depending on whether the write masking operation in the DRAM circuit is performed or not.

摘要翻译： 为了提供即使在写入操作伴随写入屏蔽操作时也能够实现高速写入操作的DRAM电路及其控制方法。 本发明的DRAM电路具有用于经由读出放大器连接位线对和数据线对的新颖的列开关。 该新颖的列开关具有在写掩模操作期间分离与所选数据线对对应的位线对的功能。 结果，即使在线对被感测放大器充分放大之前使列开关变为ON，也不必担心位线对上的数据由于读出放大器的故障而被破坏，因此 使得可以实现高速写入操作，而不依赖于是否执行DRAM电路中的写入屏蔽操作。

公开(公告)号：US06421269B1

公开(公告)日：2002-07-16

申请号：US09690687

申请日：2000-10-17

申请人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

发明人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

IPC分类号： G11C1124

CPC分类号： H01L29/66181 ,  H01L27/0218 ,  H01L27/10805 ,  H01L29/94

摘要： A planar capacitor for use within a dynamic random access memory (DRAM) cell is operated within semiconductor depletion during normal storage operations to increase the charge retention time of the capacitor. Operation within semiconductor depletion allows a significant increase in charge retention time in a capacitor for which gate oxide leakage is the predominant leakage mechanism. The voltages that are applied to the storage cell during DRAM operation are controlled so that the storage capacitor within the cell remains in depletion during storage of both a logic zero and a logic one. Although the capacitance of the cell is decreased by operating in depletion, the charge retention time of the cell can be increased by multiple orders of magnitude. In one application, the inventive structures and techniques are implemented within a DRAM device that is embedded within logic circuitry.

摘要翻译： 用于动态随机存取存储器（DRAM）单元的平面电容器在正常存储操作期间在半导体耗尽中运行，以增加电容器的电荷保留时间。 在半导体耗尽中的操作允许在电容器中的电荷保持时间显着增加，其中栅极氧化物泄漏是主要的泄漏机制。 控制在DRAM操作期间施加到存储单元的电压，使得在存储逻辑0和逻辑1期间，单元内的存储电容器保持耗尽。 尽管电池的电容通过在耗尽中操作而降低，但电池的电荷保持时间可以增加多个数量级。 在一个应用中，本发明的结构和技术在嵌入在逻辑电​​路内的DRAM器件内实现。