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    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IN-MEMORY COMPUTING METHOD
    1.
    发明公开
    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IN-MEMORY COMPUTING METHOD 审中-公开

    公开(公告)号：US20240355387A1

    公开(公告)日：2024-10-24

    申请号：US18303726

    申请日：2023-04-20

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Yu-Yu LIN ,  Feng-Min LEE

    IPC分类号： G11C13/00

    CPC分类号： G11C13/004 ,  G11C13/0026 ,  G11C13/0061

    摘要： An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

    VOLTAGE-MODE CROSSBAR CIRCUITS
    2.
    发明公开
    VOLTAGE-MODE CROSSBAR CIRCUITS 审中-公开

    公开(公告)号：US20240355386A1

    公开(公告)日：2024-10-24

    申请号：US18302278

    申请日：2023-04-18

    申请人： TetraMem Inc.

    发明人： Hengfang Zhu ,  Wenbo Yin ,  Miao Hu

    IPC分类号： G11C13/00

    CPC分类号： G11C13/003 ,  G11C13/004 ,  G11C2213/79

    摘要： The present disclosure relates to voltage-mode crossbar circuits that may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and a plurality of sensing circuits configured to amplify bit line voltages settled on the bit lines in response to an application of input voltages to the cross-point devices via the word lines and generate digital outputs representative of the amplified bit line voltages. Each cross-point device is connected to one of the word lines and one of the bit lines and may include a resistive random-access memory (RRAM) device. Each cross-point device may further be connected to a local select line that may enable a group of cross-point devices connected to one or more bit lines. A cross-point device may be enabled when both a global select line and the local select line connected to the cross-point device are enabled.

    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING
    3.
    发明公开
    MEMORY INCLUDING METAL RAILS WITH BALANCED LOADING 审中-公开

    公开(公告)号：US20240331771A1

    公开(公告)日：2024-10-03

    申请号：US18741201

    申请日：2024-06-12

    申请人： Taiwan Semiconductor Manufacturing Company Ltd.

    发明人： Meng-Sheng Chang ,  Chia-En HUANG ,  Yi-Ching LIU ,  Yih WANG

    IPC分类号： G11C13/00

    CPC分类号： G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

    摘要： Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

    Multi-step pre-read for write operations in memory devices
    4.
    发明授权
    Multi-step pre-read for write operations in memory devices 有权

    公开(公告)号：US12106803B2

    公开(公告)日：2024-10-01

    申请号：US17824776

    申请日：2022-05-25

    申请人： Micron Technology, Inc.

    发明人： Yen Chun Lee ,  Nevil N. Gajera ,  Karthik Sarpatwari

    IPC分类号： G11C11/4074 ,  G11C13/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0076

    摘要： Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

    METHOD FOR PROCESSING INPUT VARIABLES BY MEANS OF A PROCESSING DEVICE HAVING AT LEAST ONE TRANSISTOR, DEVICE FOR EXECUTING THE METHOD, COMPUTING DEVICE AND USE
    5.
    发明公开
    METHOD FOR PROCESSING INPUT VARIABLES BY MEANS OF A PROCESSING DEVICE HAVING AT LEAST ONE TRANSISTOR, DEVICE FOR EXECUTING THE METHOD, COMPUTING DEVICE AND USE 审中-公开

    公开(公告)号：US20240313779A1

    公开(公告)日：2024-09-19

    申请号：US18600281

    申请日：2024-03-08

    申请人： Robert Bosch GmbH

    发明人： Taha Soliman ,  Tobias Kirchner

    IPC分类号： H03K19/0948 ,  G11C13/00

    CPC分类号： H03K19/0948 ,  G11C13/0002

    摘要： A method for processing input variables by means of a processing device having least a first transistor. The method including: providing the first transistor and a first memristive element, which characterizes a first input variable associated with the first transistor, wherein a charging current of a capacitance associated with a control electrode of the first transistor can be influenced using the first memristive element; applying to the control electrode of the first transistor a first output variable which characterizes a second input variable associated with the first transistor; ascertaining a first output variable which characterizes at least one product of the first input variable and of the second input variable, based on a first variable characterizing a time profile of a current through a load path of the first transistor.

    ERASE ALGORITHM WITH A WEAK PROGRAM PULSE FOR NON-VOLATILE MEMORY
    6.
    发明公开
    ERASE ALGORITHM WITH A WEAK PROGRAM PULSE FOR NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20240304243A1

    公开(公告)日：2024-09-12

    申请号：US18119104

    申请日：2023-03-08

    申请人： Crossbar, Inc.

    发明人： Zhi Li ,  Sung Hyun Jo ,  Jordan Frick

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0097 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069

    摘要： Improved erase techniques and apparatuses can improve performance and longevity of non-volatile memory. Various disclosed techniques include performing an erase operation(s) on a group of such memory cells, followed by a weak program operation. One or more subsequent erase-verify operations can be implemented until no erase disturb states are detected for the memory cells, or until a maximum erase-verify cycle count is reached. In one or more embodiments, additional weak program and erase-verify cycles can be implemented to enhance cycle longevity and reduce erase disturb states for the group of non-volatile memory.

    Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement
    8.
    发明授权
    Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement 有权

    公开(公告)号：US12080347B1

    公开(公告)日：2024-09-03

    申请号：US17710835

    申请日：2022-03-31

    申请人： Crossbar, Inc.

    发明人： Hagop Nazarian

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004

    摘要： Differential programming of multiple resistive switching memory cells defining a bit is disclosed. The differential programming can mitigate invalid data values for the defined bit, referred to herein as an identifier bit. Embodiments of the present disclosure provide for detection of a program event(s) for a portion of resistive switching memory cells defining an identifier bit, and disconnecting a remainder of the memory cells from program supply voltage, prior to a duration of a program cycle. Additionally, the program cycle can be continued for the programmed memory cell(s) to facilitate a robust programming and enhance data longevity. The detection and subsequent disconnection can facilitate proper differential programming and mitigate unwanted program events that lead to invalid identifier bit results, as well as reducing power consumption for a program cycle of resistive switching memory.