公开(公告)号：US12131776B2

公开(公告)日：2024-10-29

申请号：US17695578

申请日：2022-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zheng-Jun Lin ,  Chin-I Su ,  Chung-Cheng Chou ,  Chia-Fu Lee

IPC分类号： G11C14/00 ,  G11C11/412 ,  G11C11/419 ,  H03K19/20 ,  G11C13/00 ,  H03K19/21

CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C14/009 ,  H03K19/20 ,  G11C13/0026 ,  H03K19/21

摘要： A memory device including a static random-access memory that includes two cross-coupled inverters and an access transistor having a gate connected to a word line. The memory device further includes one or more logic gates electrically coupled to the static random-access memory, and a non-volatile memory electrically coupled to the static random-access memory and configured to store data and be read using the static random-access memory, wherein the non-volatile memory is connected on one side to the access transistor and on another side to the two cross-coupled inverters.

公开(公告)号：US20240282375A1

公开(公告)日：2024-08-22

申请号：US18448164

申请日：2023-08-11

申请人： SK hynix Inc.

发明人： Seung Han RYU ,  Sung Geun KANG ,  Hyeong Rak KIM

IPC分类号： G11C14/00 ,  G06F3/06

CPC分类号： G11C14/0018 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0658 ,  G06F3/0679

摘要： According to the present technology, a storage device includes a nonvolatile storage area including a plurality of backup memory blocks each including a plurality of memory cells respectively connected to a plurality of word lines, and a controller configured to control the nonvolatile storage area to determine a target memory block in which data is to be stored among the plurality of backup memory blocks, determine a reference word line among the plurality of word lines coupled to the target memory block, and perform a pre-conditioning operation of programming dummy data to memory cells connected to at least one of remaining word lines except for the reference word line among the plurality of word lines coupled to the target memory block.

公开(公告)号：US20240272835A1

公开(公告)日：2024-08-15

申请号：US18645761

申请日：2024-04-25

申请人： Micron Technology, Inc.

发明人： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand ,  Samir Mittal

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/28 ,  G06F15/173 ,  G11C14/00 ,  H04L67/1097

CPC分类号： G06F3/067 ,  G06F12/00 ,  G06F13/28 ,  G06F15/17331 ,  G11C14/0009 ,  H04L67/1097

摘要： A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

公开(公告)号：US12019919B2

公开(公告)日：2024-06-25

申请号：US17939333

申请日：2022-09-07

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Yue Ping Li ,  Chun Yuan Hou

IPC分类号： G06F3/06 ,  G06F12/0868 ,  G11C14/00 ,  G11C16/04 ,  G11C16/10 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H10B10/00 ,  H10B41/27 ,  H10B43/27 ,  G11C11/56 ,  H10B41/40 ,  H10B43/40

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/068 ,  G06F12/0868 ,  G11C14/0063 ,  G11C16/0483 ,  G11C16/10 ,  H01L24/05 ,  H01L24/32 ,  H01L25/18 ,  H01L25/50 ,  H10B10/12 ,  H10B41/27 ,  H10B43/27 ,  G06F2212/1032 ,  G06F2212/281 ,  G11C11/5621 ,  G11C11/5671 ,  H01L2224/32145 ,  H10B41/40 ,  H10B43/40

摘要： A three-dimensional (3D) memory device includes a 3D NAND memory array, an on-die static random-access memory (SRAM), and peripheral circuits formed on the same chip with the on-die SRAM. The peripheral circuits include a page buffer coupled to the on-die SRAM and a controller coupled to the on-die SRAM and the page buffer. The controller may be configured to load program data into the page buffer and cache the program data into the on-die SRAM as a backup copy of the program data. In response to a status of programming the program data from the page buffer into the 3D NAND memory array being failed, the controller may be further configured to transmit the backup copy of the program data in the on-die SRAM to the page buffer, and program the backup copy of the program data in the page buffer into the 3D NAND memory array.

公开(公告)号：US11954031B2

公开(公告)日：2024-04-09

申请号：US17888292

申请日：2022-08-15

申请人： Kioxia Corporation

发明人： David Symons ,  Ezequiel Alves

IPC分类号： G06F12/08 ,  G06F12/0804 ,  G11C14/00

CPC分类号： G06F12/0804 ,  G06F2212/1032 ,  G11C14/0018

摘要： A method performed by a controller comprising assigning a first status indicator to entries in a first address line in a volatile memory belonging to a first region of an LUT stored in a non-volatile memory, and a second status indicator to entries in the first address line in the volatile memory belonging to a second region of the LUT, setting either the first or second status indicator to a dirty status based on whether a cache updated entry at an address m in the volatile memory belongs to the first or second region of the LUT, and writing, based on the dirty status of the first and second status indicator at the address m, all entries in the volatile memory associated with the first region or the second region containing the updated entry to the non-volatile memory.

公开(公告)号：US11929117B2

公开(公告)日：2024-03-12

申请号：US17384143

申请日：2021-07-23

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Xuwen Pan

IPC分类号： G11C11/00 ,  G11C11/412 ,  G11C13/00 ,  G11C14/00 ,  H10B10/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： G11C13/0004 ,  G11C11/412 ,  G11C13/004 ,  G11C14/009 ,  H10B10/12 ,  H10N70/231 ,  H10N70/826

摘要： In certain aspects, a memory device includes a bit line, a plurality of memory cells coupled with the bit line, and N selectors, where N is a positive integer greater than 1, and N word lines. Each one of the plurality of memory cells includes N phase-change memory (PCM) elements. Each one of the N selectors is coupled with a respective one of the N PCM elements. Each one of the N word lines is coupled with a respective one of the N selectors.

公开(公告)号：US11881263B2

公开(公告)日：2024-01-23

申请号：US17221670

申请日：2021-04-02

申请人： Arm Limited

发明人： Akhilesh Ramlaut Jaiswal ,  Mudit Bhargava

IPC分类号： G11C14/00 ,  G11C11/16 ,  G11C11/418 ,  G11C11/419 ,  H01F10/32 ,  G11C13/00 ,  H10N50/80 ,  H10N50/85

CPC分类号： G11C14/0081 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/418 ,  G11C11/419 ,  G11C11/161 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C14/009 ,  G11C2213/31 ,  G11C2213/32 ,  H01F10/329 ,  H01F10/3254 ,  H10N50/80 ,  H10N50/85

摘要： Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

公开(公告)号：US11880569B2

公开(公告)日：2024-01-23

申请号：US18303127

申请日：2023-04-19

申请人： Mosaid Technologies Incorporated

发明人： Peter B. Gillingham ,  Graham Allan

IPC分类号： G11C8/00 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00 ,  H03K5/00

CPC分类号： G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/00

摘要： A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

公开(公告)号：US11864367B2

公开(公告)日：2024-01-02

申请号：US17228496

申请日：2021-04-12

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Weihua Cheng ,  Jun Liu

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  G11C14/00 ,  G11C16/04 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06 ,  H01L29/04 ,  H01L29/16 ,  H01L21/76 ,  H10B12/00 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： H10B10/12 ,  G11C14/0018 ,  G11C16/0483 ,  H01L21/02013 ,  H01L21/2007 ,  H01L21/50 ,  H01L21/76 ,  H01L21/8221 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/04 ,  H01L29/16 ,  H10B12/02 ,  H10B12/033 ,  H10B12/05 ,  H10B12/09 ,  H10B12/31 ,  H10B12/50 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/08145 ,  H01L2224/291 ,  H01L2224/32145 ,  H01L2224/73215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83895 ,  H01L2224/83896

摘要： First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US20230409205A1

公开(公告)日：2023-12-21

申请号：US18339812

申请日：2023-06-22

申请人： Rambus Inc.

发明人： Aws Shallal ,  Micheal Miller ,  Stephen Horn

IPC分类号： G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16

CPC分类号： G06F3/0613 ,  G06F3/0611 ,  G11C14/0009 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1441 ,  G06F11/00 ,  G11C5/04 ,  G11C11/005 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0802 ,  G06F13/1673 ,  G06F13/1668 ,  G11C7/1051

摘要： Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.