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公开(公告)号：US20250069665A1
公开(公告)日：2025-02-27
申请号：US18948059
申请日：2024-11-14
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Xueqing Huang , Wei Huang , Xing Zhou , Chan Wang , Kang Li , Cong Luo , Fengxiang Gao
Abstract: A memory device includes a memory block including memory strings, bit lines coupled to the memory strings, dummy word lines coupled to the dummy cells, first select lines coupled to the first select transistors, and a peripheral circuit coupled to the bit lines, the dummy word lines, and the first select lines. Each of the memory strings includes memory cells, first select transistors, and dummy cells. The peripheral circuit is configured to apply a turn on voltage on the first select lines, and apply a program voltage on a first dummy word line of the dummy word lines to program all dummy cells coupled to the first dummy word line.
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2.发明申请公开(公告)号：US20250069663A1
公开(公告)日：2025-02-27
申请号：US18632972
申请日：2024-04-11
Applicant: SK hynix Inc.
Inventor： Chi Wook AN
Abstract: A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation of storing data in the plurality of memory cells; and a program operation control circuit for, in the program operation, controlling the peripheral circuit to perform a foggy program operation of increasing a threshold voltage of the plurality of memory cells to a threshold voltage corresponding to any one state among an erase state and first to sixth foggy program states, and perform a fine program operation of increasing the threshold voltage of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states.
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公开(公告)号：US20250069660A1
公开(公告)日：2025-02-27
申请号：US18454144
申请日：2023-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tal PHILOSOF , Lior KISSOS , Ariel DOUBCHAK , Amit BERMAN
Abstract: Provided are a memory system, a method of reading data and a method of finding read thresholds. The method of finding read thresholds includes: selecting a channel distribution among a plurality of channel distributions that corresponds to a read page of the memory device to be read in response to a read command; generating a Trellis diagram based on a decoding scheme and a type of the read page; determining an optimal path through the Trellis diagram using the selected channel distribution according to a dynamic programming algorithm; and finding the read thresholds from the optimal path.
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公开(公告)号：US20250061951A1
公开(公告)日：2025-02-20
申请号：US18795606
申请日：2024-08-06
Applicant: eMemory Technology Inc.
Inventor： Yu-Hsuan CHENG
Abstract: A control gate voltage generating circuit for a non-volatile memory is provided. After the non-volatile memory leaves the factory, the control gate voltage is appropriately adjusted by the control gate voltage generating circuit according to the characteristics changes of the memory cells. When the read action is performed, the control gate voltage generating circuit provides the adjusted control gate voltage to the control gate line of the array structure. The magnitude of the reference current can be maintained in the range between the read current in the erase state and the read current in the program state. Consequently, the storage state of the selected memory cell can be accurately determined, and the life time of the non-volatile memory will be extended.
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公开(公告)号：US12230349B2
公开(公告)日：2025-02-18
申请号：US18129585
申请日：2023-03-31
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta
Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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Patent Agency Ranking
公开(公告)号：US12230334B2
公开(公告)日：2025-02-18
申请号：US17710978
申请日：2022-03-31
Applicant: Intel NDTM US LLC
Inventor： Aliasgar S. Madraswala , Ali Khakifirooz , Bhaskar Venkataramaiah , Sagar Upadhyay , Yogesh B. Wakchaure
Abstract: Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.
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公开(公告)号：US12230328B2
公开(公告)日：2025-02-18
申请号：US17868900
申请日：2022-07-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun Seo
Abstract: A semiconductor device includes a cell area including a plurality of word lines stacked on a substrate, at least one ground select line between the plurality of word lines and substrate, and a plurality of channel structures passing through the plurality of word lines and the at least one ground select line, and a peripheral circuit area including peripheral circuits controlling the cell area. The peripheral circuits input a first ground select bias voltage to the at least one ground select line during a first program time to a program word line selected from among the plurality of word lines, and input a second ground select bias voltage having a magnitude different from the first ground select bias voltage to the at least one ground select line during a second program time, the second program voltage different from the first program voltage.
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公开(公告)号：US20250054556A1
公开(公告)日：2025-02-13
申请号：US18231368
申请日：2023-08-08
Applicant: Western Digital Technologies, Inc.
Inventor： Jiacen Guo , Xiang Yang , Henry Chin
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.
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公开(公告)号：US20250054555A1
公开(公告)日：2025-02-13
申请号：US18232010
申请日：2023-08-09
Applicant: Western Digital Technologies, Inc.
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage. A control means is coupled to the plurality of word lines and is configured to apply at least one programming pulse of a program voltage to selected ones of the plurality of word lines during at least one programming loop of a programming operation. The control means is also configured to reduce the threshold voltage of the memory cells targeted for an erased state during a bit-level erase operation following the programming operation.
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公开(公告)号：US20250054550A1
公开(公告)日：2025-02-13
申请号：US18366572
申请日：2023-08-07
Applicant: Western Digital Technologies, Inc.
Inventor： Jiahui Yuan , Henry Chin , Changyuan Chen
Abstract: A non-volatile memory is configured to transition blocks of non-volatile memory cells between full block mode and sub-block mode.
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