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公开(公告)号：US20240363168A1
公开(公告)日：2024-10-31
申请号：US18230336
申请日：2023-08-04
发明人： Abhijith Prakash , Xiang Yang
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
摘要： The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.
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公开(公告)号：US12125532B2
公开(公告)日：2024-10-22
申请号：US17459172
申请日：2021-08-27
发明人： Laurent Murillo
CPC分类号： G11C16/0433 , G11C16/102 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/30
摘要： In an embodiment an electrically erasable programmable readable memory includes a plurality of memory cells organised in a memory plane arranged in a matrix fashion in rows and in columns, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window situated on the side of the drain, a control gate and a floating gate and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.
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3.发明公开公开(公告)号：US20240347113A1
公开(公告)日：2024-10-17
申请号：US18752870
申请日：2024-06-25
申请人： KIOXIA CORPORATION
发明人： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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公开(公告)号：US12112807B2
公开(公告)日：2024-10-08
申请号：US17902725
申请日：2022-09-02
申请人： KIOXIA CORPORATION
发明人： Mina Hatakeyama
摘要： A semiconductor storage device includes a circuit, a first plurality of conductive layers arranged along a first direction, extending along a second direction, and including first through third layers, the first layer between the second and third layers, a second plurality of conductive layers including fourth through sixth layers corresponding to the first through third layers and separated therefrom, a semiconductor layer extending between the first and second pluralities, and a charge storage layer between the semiconductor layer and the first and second pluralities. The circuit applies, in a verification operation of a write operation on the first conductive layer, a verification voltage to the first layer, a voltage smaller than the verification voltage to the fourth layer, a read voltage larger than the verification voltage to the second and fifth conductive layers, and a second voltage smaller than the read voltage to the third or sixth conductive layer.
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5.发明公开公开(公告)号：US20240312949A1
公开(公告)日：2024-09-19
申请号：US18306971
申请日：2023-04-25
发明人： Kang-Yun Yang , Yang-Tse Hung , Chao-Cheng Ku , Li-Yuan Lee
CPC分类号： H01L24/49 , G11C5/06 , G11C16/14 , H01L2224/4912
摘要： A layout structure of differential lines, a memory storage device and a memory control circuit unit are provided. The layout structure of the differential lines includes a wiring layer, a first wire and a second wire. The first wire is arranged on the wiring layer and configured to transmit a first differential signal. The second wire is arranged on the wiring layer and configured to transmit a second differential signal. A first end of the first wire and a first end of the second wire are coupled to a first electrical component. A second end of the first wire and a second end of the second wire are coupled to a second electrical component. The first end of the first wire has a first bending structure. One of the second end of the first wire and the second end of the second wire has a second bending structure.
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公开(公告)号：US12040025B2
公开(公告)日：2024-07-16
申请号：US17675392
申请日：2022-02-18
发明人： Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Patrick R. Khayat , Hyung Seok Kim , Steven Michael Kientz
CPC分类号： G11C16/26 , G06F11/073 , G06F11/0787 , G11C16/14 , G11C16/0483
摘要： A system includes a memory device including an block and a processing device, operatively coupled with the memory device, to perform operations including initiating a page scan with respect to a page of the block, determining whether to perform an erased page check, and in response to determining that the erased page check is not to be performed, performing a two-sided page scan with calibration feedback.
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公开(公告)号：US20240221840A1
公开(公告)日：2024-07-04
申请号：US18604858
申请日：2024-03-14
发明人： Ezra Edward Hartz
CPC分类号： G11C16/14 , G11C16/102 , G11C16/26 , G11C16/30 , G11C16/3404
摘要： A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic causes first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first voltage distribution programmed relative to a first threshold voltage (Vt) level. The control logic causes, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second voltage distribution programmed relative to a second Vt level, wherein the second Vt level is higher than the first Vt level.
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公开(公告)号：US12020757B2
公开(公告)日：2024-06-25
申请号：US17550234
申请日：2021-12-14
申请人： SK hynix Inc.
发明人： Won Jae Choi , Min Su Kim , Hyun Chul Cho
CPC分类号： G11C16/32 , G11C16/102 , G11C16/14 , G11C16/26 , G11C16/30
摘要： A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.
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9.发明授权公开(公告)号：US12020754B2
公开(公告)日：2024-06-25
申请号：US17878933
申请日：2022-08-02
发明人： Po-Yuan Tang
CPC分类号： G11C16/20 , G11C7/14 , G11C16/0408 , G11C16/102 , G11C16/14 , G11C16/28 , G11C16/34 , G11C2211/5634
摘要： A non-volatile memory device includes a set of memory cells, a cycle transistor, a reference transistor and a control circuit. The control circuit is coupled to the set of memory cells, the cycle transistor and the reference transistor. A method of controlling the non-volatile memory device includes in a program operation or an erase operation of the set of memory cells, the control circuit determining a state of the cycle transistor, and upon determining the cycle transistor being in an erased state (or a programmed state), the control circuit setting the reference transistor from a reference state to the erased state (or the programmed state), and then restoring the reference transistor from the erased state (or the programmed state) to the reference state. The reference state is set between the erased state and a programmed state.
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公开(公告)号：US20240206170A1
公开(公告)日：2024-06-20
申请号：US18352012
申请日：2023-07-13
发明人： Satoshi SHIMIZU , Yanli ZHANG , Johann ALSMEIER
摘要： A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.
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