利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

496 records (took 0.044 seconds)

    MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM AND READABLE STORAGE MEDIUM
    1.
    发明申请
    MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM AND READABLE STORAGE MEDIUM 有权

    公开(公告)号：US20250061946A1

    公开(公告)日：2025-02-20

    申请号：US18540350

    申请日：2023-12-14

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Zhijiu ZHU

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/20 ,  G11C16/32

    Abstract: Examples of the present disclosure provide a memory and operating method thereof, a memory system and a readable storage medium. The memory includes an array of memory cells and a peripheral circuit coupled to the array of memory cells; the peripheral circuit is configured to: receive a program command, a program address, program data, and a program confirmation command which correspond to a program operation, and perform the program operation on the array of memory cells after performing at least two initialization operations. The process of receiving the program command, the program address, the program data, and the program confirmation command which correspond to the program operation and the process of performing the at least two initialization operations at least partially overlap in time.

    SMALL-AREA COMMON-VOLTAGE MULTI-WRITE NON-VOLATILE MEMORY ARRAY
    2.
    发明申请
    SMALL-AREA COMMON-VOLTAGE MULTI-WRITE NON-VOLATILE MEMORY ARRAY 有权

    公开(公告)号：US20250017005A1

    公开(公告)日：2025-01-09

    申请号：US18480722

    申请日：2023-10-04

    Applicant: YIELD MICROELECTRONICS CORP.

    Inventor： YU-TING HUANG ,  CHI-PEI WU

    IPC: H10B41/70 ,  G11C16/04 ,  G11C16/10 ,  G11C16/20 ,  G11C16/26 ,  H10B41/35

    Abstract: A small-area common-voltage multi-write non-volatile memory array includes word lines, select lines, common-voltage lines, and sub-memory arrays. The word lines include a first word line and a second word line. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each sub-memory array includes a first non-volatile memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second non-volatile memory cell coupled to the second word line, the first select line, and the second common-voltage line.

    MEMORY DEVICE INCLUDING THREE DIMENSIONAL ARRAY STRUCTURE AND OPERATING METHOD THEREOF
    4.
    发明公开
    MEMORY DEVICE INCLUDING THREE DIMENSIONAL ARRAY STRUCTURE AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240212754A1

    公开(公告)日：2024-06-27

    申请号：US18321001

    申请日：2023-05-22

    Applicant: SK hynix Inc.

    Inventor： KyuSub YOON

    IPC: G11C16/04 ,  G11C16/20 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C16/20 ,  G11C16/26

    Abstract: A memory device comprises a memory cell array comprising multiple memory cells that are connected between multiple word lines, multiple bit lines, and K strings, and a controller configured to: perform, in a read operation on a first logical page of a selected physical page corresponding to a selected word line, the multiple bit lines and a selected string, a first channel-initializing operation on the selected string and first strings among unselected strings, and perform, in a read operation on a second logical page of the selected physical page, a second channel-initializing operation on the selected string and second strings among the unselected strings, the first and second strings partially overlapping each other, wherein K is a natural number equal to or greater than 2.

    MEMORY SYSTEM
    10.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20230122474A1

    公开(公告)日：2023-04-20

    申请号：US18086206

    申请日：2022-12-21

    Applicant: KIOXIA CORPORATION

    Inventor： Noboru Okamoto ,  Toshikatsu Hida

    IPC: G06F11/10 ,  G11C16/26 ,  G11C16/20 ,  G11C16/04

    Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

Patent Agency Ranking