公开(公告)号：US12130655B2

公开(公告)日：2024-10-29

申请号：US18508479

申请日：2023-11-14

申请人： Samsung Electronics Co., Ltd.

发明人： Kwanwoo Noh ,  Sungho Seo ,  Yongwoo Jeong ,  Dongwoo Nam ,  Myungsub Shin ,  Hyunkyu Jang

IPC分类号： G06F1/08 ,  G06F1/04 ,  G06F3/06 ,  G06F13/42 ,  G11C7/22 ,  G11C16/32 ,  H04L7/00

CPC分类号： G06F1/08 ,  G06F1/04 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0679 ,  G06F13/4291 ,  G11C7/22 ,  G11C16/32 ,  H04L7/0004 ,  H04L7/0008

摘要： A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US12100459B2

公开(公告)日：2024-09-24

申请号：US18333661

申请日：2023-06-13

申请人： KIOXIA CORPORATION

发明人： Shinya Okuno ,  Shigeki Nagasaka ,  Toshiyuki Kouchi

IPC分类号： G11C16/04 ,  G06F5/06 ,  G06F13/16 ,  G11C7/02 ,  G11C7/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC分类号： G11C16/32 ,  G06F5/06 ,  G06F13/1673 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G06F2205/067 ,  G11C16/0483 ,  G11C2207/108 ,  G11C2207/2281 ,  Y02D10/00

摘要： A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

公开(公告)号：US12100458B2

公开(公告)日：2024-09-24

申请号：US17827562

申请日：2022-05-27

申请人： SanDisk Technologies LLC

发明人： Venkatesh Prasad Ramachandra ,  Jang Woo Lee ,  Srinivas Rajendra ,  Anil Pai

IPC分类号： G11C16/32

CPC分类号： G11C16/32

摘要： Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.

公开(公告)号：US20240312533A1

公开(公告)日：2024-09-19

申请号：US18677727

申请日：2024-05-29

申请人： Kioxia Corporation

发明人： Yoshihisa KOJIMA

IPC分类号： G11C16/32 ,  G11C7/04 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/32 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3495 ,  G11C2211/5648

摘要： A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

公开(公告)号：US12086465B2

公开(公告)日：2024-09-10

申请号：US17952402

申请日：2022-09-26

申请人： Kioxia Corporation

发明人： Yoshikazu Harada

IPC分类号： G11C16/32 ,  G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G11C16/10 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30

摘要： A semiconductor memory device includes a memory cell array and a control circuit configured to receive a first command set, reject a second command set related to a write operation or an erase operation, in a first time period of executing a first operation on the memory cell array in response to the first command set, receive a third command set related to a read operation in the first time period, and execute the read operation on the memory cell array in response to the third command set.

公开(公告)号：US20240282377A1

公开(公告)日：2024-08-22

申请号：US18441331

申请日：2024-02-14

申请人： Samsung Electronics Co., Ltd.

发明人： Chaehyeon LIM ,  Woojae JANG ,  Sejun PARK ,  Yujeong SEO ,  Jaeduk LEE

IPC分类号： G11C16/08 ,  G11C16/04 ,  G11C16/32

CPC分类号： G11C16/08 ,  G11C16/0433 ,  G11C16/32

摘要： Provided is an operating method of a nonvolatile memory device including a plurality of cell strings, each cell string of the plurality of cell strings including a plurality of memory cells, connected between a bit line and a common source line, and vertical holes penetrating a plurality of word lines stacked in a direction perpendicular to a substrate, the operating method including applying a word line voltage to the plurality of word lines, classifying the plurality of word lines into a plurality of regions, each region of the plurality of regions including at least one of the word lines, and recovering voltages of the plurality of word lines by recovering voltages of word lines arranged in a central region among the plurality of regions before recovering voltages of word lines in other regions of the plurality of regions.

公开(公告)号：US20240249781A1

公开(公告)日：2024-07-25

申请号：US18541839

申请日：2023-12-15

申请人： Samsung Electronics Co., Ltd.

发明人： Keiichi KUSHIDA

IPC分类号： G11C16/32 ,  G11C16/30

CPC分类号： G11C16/32 ,  G11C16/30

摘要： A clock signal generator includes a power voltage providing circuit configured to provide a power voltage changing according to a temperature based on a temperature coefficient, a first reference voltage providing circuit configured to provide a first reference voltage based on an internal power voltage, and a clock signal generating circuit configured to generate a clock signal based on the power voltage and the first reference voltage.

公开(公告)号：US20240233839A9

公开(公告)日：2024-07-11

申请号：US18489770

申请日：2023-10-18

申请人： Micron Technology, Inc.

发明人： Chiara Cerafogli ,  Kenneth William Marr ,  Marco Domenico Tiburzi ,  Matthew Joseph Iriondo ,  Warren Lee Boyer ,  Brian James Soderling ,  James Eric Davis ,  Fulvio Rori

IPC分类号： G11C16/32

CPC分类号： G11C16/32 ,  G01K13/00

摘要： A digital thermometer includes a first oscillator to generate a first clock signal, wherein a period of the first clock signal remains constant in view of changes in a temperature of the apparatus and a first counter coupled to the first oscillator, the first counter to count a fixed number of cycles of the first clock signal associated with a measurement period. The digital thermometer further includes a second oscillator to generate a second clock signal, wherein a period of the second clock signal varies with changes in the temperature and a second counter coupled to the second oscillator, the second counter to generate an output representing a count of a number of cycles of the second clock signal that occur during the measurement period. In addition, the digital thermometer includes calibration circuitry coupled to the second counter, the calibration circuitry to calibrate the output of the second counter to generate a value representing the temperature of the apparatus.

公开(公告)号：US12027214B2

公开(公告)日：2024-07-02

申请号：US17949255

申请日：2022-09-21

申请人： eMemory Technology Inc.

发明人： Che-Wei Chang

IPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

摘要： A sensing device for a non-volatile memory includes a reference circuit, two switches, a sensing circuit and a judging circuit. The reference circuit is connected to a first node. A first terminal of the first switch is connected with the first node and a control terminal of the first switch receives an inverted reset pulse. A first terminal of the second switch is connected with the first node, a second terminal of the second switch receives a ground voltage, and a control terminal of the second switch receives a reset pulse. The sensing circuit is connected between the second terminal of the first switch and a second node. The sensing circuit generates a first sensed current. The judging circuit is connected to the second node. The judging circuit receives the first sensed current and generates an output data according to the first sensed current.

公开(公告)号：US12027211B2

公开(公告)日：2024-07-02

申请号：US17825439

申请日：2022-05-26

申请人： MICRON TECHNOLOGY, INC.

发明人： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang

IPC分类号： G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

CPC分类号： G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3404

摘要： A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.