公开(公告)号：US20230049378A1

公开(公告)日：2023-02-16

申请号：US17536414

申请日：2021-11-29

申请人： eMemory Technology Inc.

发明人： Lun-Chun CHEN ,  Jiun-Ren CHEN ,  Ping-Lung HO ,  Hsin-Ming CHEN

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/30 ,  G11C16/04 ,  G11C17/08

摘要： An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

公开(公告)号：US11437082B2

公开(公告)日：2022-09-06

申请号：US16876092

申请日：2020-05-17

申请人： HeFeChip Corporation Limited

发明人： Geeng-Chuan Chern

IPC分类号： G11C7/24 ,  G11C11/419 ,  H04L9/32 ,  G06F21/72 ,  G11C17/08 ,  G11C8/20

摘要： A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.

公开(公告)号：US10892027B2

公开(公告)日：2021-01-12

申请号：US16543546

申请日：2019-08-17

申请人： Micron Technology, Inc.

发明人： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC分类号： G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C16/08 ,  G11C16/22 ,  G11C11/22 ,  G11C13/00 ,  G11C11/16

摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

公开(公告)号：US20200082894A1

公开(公告)日：2020-03-12

申请号：US16399939

申请日：2019-04-30

申请人： NXP B.V.

发明人： Jainendra Singh ,  Jwalant Kumar Mishra ,  Patrick Van de Steeg

IPC分类号： G11C17/08 ,  G11C8/08 ,  G11C11/417 ,  G11C11/412

摘要： A read-only memory (ROM) includes ROM cells and a bias control circuit for biasing the ROM cells. Each ROM cell includes a set of transistors. The bias control circuit is connected to body terminals of the transistors of each ROM cell to provide a bias voltage. The bias voltage, which is temperature-dependent, is generated based on junction leakages at the body terminals of the transistors. The bias control circuit controls threshold voltages of the transistors using the bias voltage. The use of a temperature-dependent bias voltage to bias the body terminals of the transistors allows for a relatively constant read margin for each ROM cell.

公开(公告)号：US20180366205A1

公开(公告)日：2018-12-20

申请号：US16112402

申请日：2018-08-24

申请人： Texas Instruments Incorporated

发明人： Stephen Keith Heinrich-Barna ,  Raviprakash Suryanarayana Rao

IPC分类号： G11C17/08 ,  G11C7/18 ,  G11C16/04 ,  G11C16/30 ,  G11C16/26

摘要： A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

公开(公告)号：US10032487B2

公开(公告)日：2018-07-24

申请号：US15086767

申请日：2016-03-31

申请人： ARM Ltd.

发明人： Lucian Shifren ,  Robert Campbell Aitken ,  Vikas Chandra ,  Bal S. Sandhu

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C13/00 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18

摘要： An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to the CES element to program the CES element to an impedance state of multiple impedance states when a number of times the CES element has been programed is less than a threshold.

公开(公告)号：US20170278582A1

公开(公告)日：2017-09-28

申请号：US15143160

申请日：2016-04-29

申请人： Broadcom Corporation

发明人： Dechang SUN ,  Wei ZHANG ,  Mai T. MAC LENNAN ,  Sudeep Ashok POMAR ,  Roy M. CARLSON

IPC分类号： G11C17/08

CPC分类号： G11C17/14 ,  G11C7/067 ,  G11C7/12 ,  G11C7/18 ,  G11C11/5692 ,  G11C14/00 ,  G11C17/08 ,  G11C17/10

摘要： Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

公开(公告)号：US20170243659A1

公开(公告)日：2017-08-24

申请号：US15050678

申请日：2016-02-23

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Stephen Keith Heinrich-Barna ,  Raviprakash Suryanarayana Rao

IPC分类号： G11C17/08

CPC分类号： G11C17/08 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/26 ,  G11C16/30

摘要： A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

公开(公告)号：US20170110170A1

公开(公告)日：2017-04-20

申请号：US15293422

申请日：2016-10-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： KI HO KONG ,  Chang Hee Shin ,  Hong Keun Yune ,  Jae Hyok Ko

IPC分类号： G11C7/24 ,  H01L23/528 ,  H01L27/112 ,  H01L27/02 ,  H02H9/04 ,  G11C17/08

摘要： An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.

公开(公告)号：US09548122B2

公开(公告)日：2017-01-17

申请号：US14711765

申请日：2015-05-13

申请人： eMemory Technology Inc.

发明人： Po-Hao Huang

IPC分类号： G11C16/08 ,  G11C17/16 ,  G11C17/18 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  H01L23/528 ,  H01L29/93 ,  H01L27/112 ,  H01L27/06 ,  H01L29/10 ,  H01L29/49 ,  H01L27/115 ,  H03K3/356 ,  G11C17/14 ,  G11C29/00 ,  H01L23/525

CPC分类号： G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C17/04 ,  G11C17/08 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/11206 ,  H01L27/11524 ,  H01L29/1079 ,  H01L29/4916 ,  H01L29/93 ,  H01L2924/0002 ,  H03K3/356182 ,  H01L2924/00

摘要： A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.

摘要翻译： 电平移位驱动器电路包括电平移位电路和驱动器电路。 驱动器电路包括第一和第二P型晶体管和串联耦合的第一和第二N型晶体管。 当电平移位电路的第一输入信号处于工作电压时，电平移位电路关断第二N型晶体管。 第一N型晶体管的控制端子接收工作电压，以避免第二N型晶体管的栅极引起的漏极漏电流。 当第一输入信号处于系统基极电压时，电平移位电路关断第一P型晶体管。 第二P型晶体管的控制端子接收工作电压以避免第一P型晶体管的栅极引起的漏极漏电流。