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    Semiconductor memory devices and repair methods of the semiconductor memory devices
    2.
    发明授权
    Semiconductor memory devices and repair methods of the semiconductor memory devices 有权

    公开(公告)号：US11621050B2

    公开(公告)日：2023-04-04

    申请号：US17024396

    申请日：2020-09-17

    申请人： SK hynix Inc.

    发明人： Jae Il Lim ,  Su Hae Woo

    IPC分类号： G11C29/44 ,  G11C29/38 ,  G06F11/20 ,  G11C29/16 ,  G11C29/00

    摘要： A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.

    Link evaluation for a memory device
    3.
    发明授权
    Link evaluation for a memory device 有权

    公开(公告)号：US11615862B2

    公开(公告)日：2023-03-28

    申请号：US17121314

    申请日：2020-12-14

    申请人： Micron Technology, Inc.

    发明人： Markus Balb ,  Thomas Hein ,  Heinz Hoenigschmid

    IPC分类号： G11C29/44 ,  G11C29/12 ,  G11C29/38

    摘要： Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

    DEFECTIVE MEMORY UNIT SCREENING IN A MEMORY SYSTEM
    5.
    发明申请
    DEFECTIVE MEMORY UNIT SCREENING IN A MEMORY SYSTEM 有权

    公开(公告)号：US20220406395A1

    公开(公告)日：2022-12-22

    申请号：US17895761

    申请日：2022-08-25

    申请人： Micron Technology, Inc.

    发明人： Alex Frolikov

    IPC分类号： G11C29/44 ,  G11C29/38 ,  G06F3/06 ,  G06F11/07

    摘要： A memory system having non-volatile media and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. The non-volatile media has a set of memory units. The memory system stores an indicator indicating whether the memory system is operating in a user mode or a manufacturing mode. A defect manager of the memory system identifies a threshold based on the indicator, monitors an error rate in reading data from the non-volatile media and, in response to the error rate reaching the threshold, screens the non-volatile media for defective memory units.

    On-chip memory diagnostics
    6.
    发明授权
    On-chip memory diagnostics 有权

    公开(公告)号：US11527298B1

    公开(公告)日：2022-12-13

    申请号：US17162347

    申请日：2021-01-29

    申请人： Synopsys, Inc.

    发明人： Karen Darbinyan ,  Tatevik Melkumyan ,  Yervant Zorian

    IPC分类号： G11C29/38 ,  G06F16/215 ,  G06F13/28

    摘要： An on-chip memory diagnostic (OCMD) circuit may instruct a set of built-in self-test (BIST) engines to execute BIST on memories associated with the set of BIST engines. Next, results of executing BIST on the memories may be received from the set of BIST engines. A set of memory failures may then be identified in the memories based on the results. Next, one or more BIST engines in the set of BIST engines may be instructed to collect diagnostic data for each memory failure. A set of diagnostic data may then be received for the set of memory failures. Next, the set of diagnostic data may be stored in an on-chip data container. The set of diagnostic data may then be provided via a communication channel.

    Memory sub-system self-testing operations
    7.
    发明授权
    Memory sub-system self-testing operations 有权

    公开(公告)号：US11514995B2

    公开(公告)日：2022-11-29

    申请号：US17211133

    申请日：2021-03-24

    申请人： Micron Technology, Inc.

    发明人： Nathan A. Eckel ,  Keith A. Benjamin

    IPC分类号： G11C29/12 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G11C29/48

    摘要： A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

    Memory device and method for using shared latch elements thereof
    8.
    发明授权
    Memory device and method for using shared latch elements thereof 有权

    公开(公告)号：US11495318B2

    公开(公告)日：2022-11-08

    申请号：US16891326

    申请日：2020-06-03

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Jung-Hsing Chien

    IPC分类号： G11C29/38 ,  G11C29/36 ,  H01L25/065 ,  H01L25/18 ,  G01R31/3177 ,  G11C29/50

    摘要： The present disclosure provides memory devices and methods for using shared latch elements thereof. A memory device includes a substrate, an interposer disposed over the substrate, and a logic die and stacked memory dies disposed over the interposer. In the logic die, the test generation module performs a memory test operation for the memory device. The functional elements stores functional data in latch elements during a functional mode of the memory device. The repair analysis module determines memory test/repair data based on the memory test operation. The memory test/repair data comprises memory addresses of faulty memory storage locations of the memory device that are identified during the memory test operation. The repair analysis module configures the latch elements into a scan chain, accesses the memory test/repair data during the test mode of the memory device, and repairs the memory device using the memory test/repair data.

    Testing magnetoresistive random access memory for low likelihood failure
    9.
    发明授权
    Testing magnetoresistive random access memory for low likelihood failure 有权

    公开(公告)号：US11482295B2

    公开(公告)日：2022-10-25

    申请号：US17033586

    申请日：2020-09-25

    申请人： Infinitum Solutions, Inc.

    发明人： Wade Ogle ,  Henry Patland

    IPC分类号： G11C29/38 ,  G11C29/44 ,  G11C11/16

    摘要： A Magnetoresistive Random Access Memory (MRAM) device is tested using a high repetition test that detects one or more low-likelihood failures, such as a failure to properly switch between a high or low resistive state. A series of write and read operations are performed for a large number of test cycles at high frequency. A first tier measurement is used to determine if a switching failure occurred, e.g. by comparing the read signal to target level(s) after each operation. When a switching failure event is detected, a second tier measurement is used to measure and store switching performance parameters, for example, the value of the read signal, while the MRAM device is in a failure state. The high frequency testing may be paused during the second tier measurements. Additional performance parameters may be measured during the second tier measurements.

    REDUNDANT CIRCUIT ASSIGNING METHOD AND DEVICE, AND MEDIUM
    10.
    发明申请
    REDUNDANT CIRCUIT ASSIGNING METHOD AND DEVICE, AND MEDIUM 有权

    公开(公告)号：US20220310187A1

    公开(公告)日：2022-09-29

    申请号：US17648665

    申请日：2022-01-21

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： YUI-LANG CHEN

    IPC分类号： G11C29/38

    摘要： A redundant circuit assigning method includes: executing a first test item to obtain first test data including position data of fail bits acquired during execution of the first test item; determining a first redundant circuit assigning result according to the first test data, where the first redundant circuit assigning result includes a number of assigned local redundant circuits and their corresponding position data; executing a second test item to obtain second test data including position data of fail bits acquired during execution of the second test item; and determining a second redundant circuit assigning result according to the first test data and the second test data, when the fail bits acquired during the execution of the second test item include one or more fail bits beyond a repair range of the assigned local redundant circuits and assigned global redundant circuits and when assignable local redundant circuits have been assigned.