公开(公告)号：US20240363175A1

公开(公告)日：2024-10-31

申请号：US18768926

申请日：2024-07-10

申请人： KIOXIA CORPORATION

发明人： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA

IPC分类号： G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52

CPC分类号： G11C16/34 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C16/0483

摘要： According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

公开(公告)号：US20240361922A1

公开(公告)日：2024-10-31

申请号：US18767906

申请日：2024-07-09

申请人： Kioxia Corporation

发明人： Daisuke HASHIMOTO

IPC分类号： G06F3/06 ,  G06F1/26 ,  G06F11/10 ,  G06F12/02 ,  G11C5/14 ,  G11C29/52

CPC分类号： G06F3/0619 ,  G06F3/0614 ,  G06F3/0625 ,  G06F12/0246 ,  G06F1/266 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0683 ,  G06F3/0688 ,  G06F11/1068 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/263 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C5/144 ,  G11C5/147 ,  G11C5/148 ,  G11C29/52 ,  Y02D10/00

摘要： A memory system includes an interface circuit configured to connect to a host device, a controller electrically connected to the interface circuit, and a nonvolatile semiconductor memory electrically connected to the controller. The controller is configured to transmit a first response in response to a power supplied from the host device via the interface circuit, upon receipt of a first command from the host device after transmitting the first response, determine a status of data stored in the nonvolatile semiconductor memory, and transmit to the host device a second response including the determined status of the data stored in the nonvolatile semiconductor memory.

公开(公告)号：US12132501B2

公开(公告)日：2024-10-29

申请号：US17895227

申请日：2022-08-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Wonjae Shin ,  Sung-Joon Kim ,  Heedong Kim ,  Minsu Bae ,  Ilwoong Seo ,  Mijin Lee ,  Seung Ju Lee ,  Hyan Suk Lee ,  Insu Choi ,  Kideok Han

IPC分类号： H03M13/19 ,  G06F11/10 ,  G11C5/04 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/00

CPC分类号： H03M13/19 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1048 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/611 ,  G11C5/04

摘要： A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

公开(公告)号：US12131791B2

公开(公告)日：2024-10-29

申请号：US18070606

申请日：2022-11-29

申请人： SK hynix Inc.

发明人： Byung Goo Cho

IPC分类号： G11C29/44 ,  G11C29/18 ,  G11C29/52

CPC分类号： G11C29/4401 ,  G11C29/18 ,  G11C29/52 ,  G11C2029/1802

摘要： A semiconductor system includes a controller configured to: select a plurality of fail points based on defect analysis information collected in a process stage, and provide an address designating at least one of the fail points together with a partial reset command; and a semiconductor device including a plurality of functional regions each including one or more of the fail points, the semiconductor device configured to reset, in response to the partial reset command, a sequential circuit disposed in a target functional region corresponding to the address among the functional regions.

公开(公告)号：US12131024B2

公开(公告)日：2024-10-29

申请号：US18204854

申请日：2023-06-01

申请人： Kioxia Corporation

发明人： Shinichi Kanno ,  Hiroshi Nishimura ,  Hideki Yoshida ,  Hiroshi Murayama

IPC分类号： G06F3/06 ,  G06F1/3234 ,  G06F11/10 ,  G06F12/02 ,  G11C16/04 ,  G11C16/24 ,  G11C29/52 ,  H03M13/29

CPC分类号： G06F3/0604 ,  G06F1/3275 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/2906 ,  G06F12/0246 ,  G06F2212/214 ,  G11C16/0483 ,  G11C16/24 ,  Y02D10/00

摘要： A memory system including: a nonvolatile memory; first and second decoders configured to execute first and second error correction for correcting data read from the nonvolatile memory; and a controller configured to receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command, and after receiving the first command, output data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.

公开(公告)号：US20240355371A1

公开(公告)日：2024-10-24

申请号：US18607033

申请日：2024-03-15

申请人： Micron Technology, Inc.

发明人： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C29/52

CPC分类号： G11C7/1069 ,  G11C7/222 ,  G11C29/52

摘要： Methods, systems, and devices for data path signal amplification in coupled semiconductor systems are described. A semiconductor system may implement a first die including memory arrays and a second die including a host interface. The first die may include a first portion of a data path between the memory arrays and the host interface, including a first portion of data path signal amplification circuitry. The second die may include a second portion of the data path, including a second portion of data path signal amplification circuitry. The semiconductor system may implement fine-pitch interconnection between dies to support a relatively greater quantity of signal paths of the data path which, in some examples, may support reducing or eliminating serialization/deserialization circuitry associated with coarser interconnection. In some implementations, a semiconductor system may implement a switching component operable to switch between data paths having different amplification configurations of the dies.

公开(公告)号：US12119075B2

公开(公告)日：2024-10-15

申请号：US18185198

申请日：2023-03-16

申请人： Kioxia Corporation

发明人： Avi Steiner ,  Ofir Kanter ,  Yasuhiko Kurosawa

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  G11C29/02 ,  G11C29/52 ,  H03M13/11 ,  H03M13/15

CPC分类号： G11C29/52 ,  G11C29/022 ,  G11C29/024

摘要： Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.

公开(公告)号：US12119054B2

公开(公告)日：2024-10-15

申请号：US18613466

申请日：2024-03-22

申请人： Vervain, LLC

发明人： G. R. Mohan Rao

IPC分类号： G11C11/56 ,  G06F11/10 ,  G06F12/02 ,  G11C16/16 ,  G11C16/34 ,  G11C29/00 ,  G11C29/52

CPC分类号： G11C11/5635 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G11C11/5621 ,  G11C11/5678 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/76 ,  G06F2212/7202 ,  G11C2211/5641

摘要： A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.

公开(公告)号：US12117487B2

公开(公告)日：2024-10-15

申请号：US17654918

申请日：2022-03-15

申请人： STMicroelectronics (Grenoble 2) SAS

发明人： Mark Trimmer

IPC分类号： G06F12/14 ,  G01R31/317 ,  G01R31/3185 ,  G11C29/10 ,  G06F1/24 ,  G06F9/448 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/52 ,  G11C29/54

CPC分类号： G01R31/31719 ,  G01R31/318588 ,  G06F12/1458 ,  G11C29/10

摘要： The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.

公开(公告)号：US20240339172A1

公开(公告)日：2024-10-10

申请号：US18624720

申请日：2024-04-02

申请人： Micron Technology, Inc.

发明人： Yugang Yu ,  Chun Sum Yeung ,  Pitamber Shukla

IPC分类号： G11C29/52 ,  G11C29/02

CPC分类号： G11C29/52 ,  G11C29/022 ,  G11C29/028

摘要： Aspects of the present disclosure are directed to a memory sub-system using a block family error avoidance (BFEA) scan to adjust read voltages. Three-level cell (TLC) memory stores three bits per cell. Due to variances in manufacturing and degradation over time, the actual voltages stored in the memory cells deviate from the target voltages. As a result, the comparisons between the read voltages and the stored voltages may generate erroneous results. A BFEA scan may be based on a single wordline and single page type. However, determining a single threshold voltage shift to apply to all read voltages may not compensate for all causes of voltage shifting. Accordingly, a BFEA scan may use multiple wordlines (e.g., one for each page) and determine different voltage offset values for each page. As a result, the accuracy of the read voltage applied is increased and the bit error rate (BER) is reduced.