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公开(公告)号：US12211571B2
公开(公告)日：2025-01-28
申请号：US17065462
申请日：2020-10-07
Applicant: Micron Technology, Inc.
Inventor： David W. Overgaard , Andrew P. Lyle , Glen E. Hush , Timothy P. Finkbeiner , Kristopher J. Kopel , Jonathan D. Harms
Abstract: Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device. In some examples, the processing circuitry may include an analog-to-digital conversion capability for digital communication of analog characteristics internal to the memory die.
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公开(公告)号：US12190978B2
公开(公告)日：2025-01-07
申请号：US18381883
申请日：2023-10-19
Applicant: NANYA TECHNOLOGY CORPORATION
Inventor： Cheng-Ting Hsu , Yung-Huang Liao
Abstract: The present disclosure provides a memory test system, including a tester and a processor. The tester is configured to perform a final test to the memory device to obtain a test result, and read a read-only data of the packaged memory device. The processor is coupled to the tester, configured to perform a function to transform the read-only data to a chip ID of the packaged memory device when the memory device does not pass the final test according to the test result. When the packaged memory device does not pass the final test, the processor is further configured to obtain a process history of the packaged memory device according to the chip ID.
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公开(公告)号：US12190977B2
公开(公告)日：2025-01-07
申请号：US18127775
申请日：2023-03-29
Applicant: NANYA TECHNOLOGY CORPORATION
Inventor： Cheng-Ting Hsu , Yung-Huang Liao
Abstract: The present disclosure provides a memory test system, including a tester and a processor. The tester is configured to perform a final test to the memory device to obtain a test result, and read a read-only data of the packaged memory device. The processor is coupled to the tester, configured to perform a function to transform the read-only data to a chip ID of the packaged memory device when the memory device does not pass the final test according to the test result. When the packaged memory device does not pass the final test, the processor is further configured to obtain a process history of the packaged memory device according to the chip ID.
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公开(公告)号：US20250006290A1
公开(公告)日：2025-01-02
申请号：US18343377
申请日：2023-06-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Nehal Patel
Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.
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5.发明授权
公开(公告)号：US12165728B2
公开(公告)日：2024-12-10
申请号：US17665314
申请日：2022-02-04
Applicant: Advantest Corporation
Inventor： Frank Hensel , Olaf Pöppe
IPC: G11C29/56 , G01R31/319
Abstract: The automated test equipment is configured to establish communication, e.g. by uploading a program to the DUT using a first interface, such as a debug interface or a generic interface having access to the processing unit for external control. A typical use case of the first interface is debug access to the DUT, which typically requires limited data rates. In the case of the invention the first interface is an ATE access for test execution. The first interface configures the DUT to open a second interface running at much higher data rate, which is higher than the first interface, for additional communication. Additionally, the second interface may have extended capabilities compared to the first interface, such as presenting its own memory to the processing unit of the DUT as a normal system memory.
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公开(公告)号：US20240386987A1
公开(公告)日：2024-11-21
申请号：US18211529
申请日：2023-06-19
Applicant: SQ TECHNOLOGY (SHANGHAI) CORPORATION , INVENTEC CORPORATION
Inventor： WEI-GUO ZHAO
IPC: G11C29/56
Abstract: A test system for a DRAM module of an AMD system is configured to verify information write and read functions of an EEPROM included in the DRAM module. The test system includes at least one memory module slot and a processing unit. The at least one memory module slot is configured for insertion of the DRAM module. The DRAM module includes the EEPROM. After an operating system controlling the processing unit, an I2C operation register of the processing unit can access the DRAM module through an I2C bus, and can write test data to and read the test data from the EEPROM. When the test data does not have sample data, it can be replaced by serial presence detection information.
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公开(公告)号：US12142340B2
公开(公告)日：2024-11-12
申请号：US17814232
申请日：2022-07-22
Applicant: Realtek Semiconductor Corporation
Inventor： Shih-Chieh Lin , Sheng-Lin Lin , Li-Wei Deng
Abstract: A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.
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公开(公告)号：US12106816B2
公开(公告)日：2024-10-01
申请号：US17790472
申请日：2022-05-09
Applicant: ChangXin Memory Technologies, Inc.
IPC: G11C29/56
CPC classification number: G11C29/56016 , G11C29/56004
Abstract: The present disclosure provide latch performance detecting method and a device. The method includes: extracting circuit structure information of a latch, having a transmission gate and a latch unit, an output terminal of the transmission gate is coupled to the input terminal of the latch unit, and the input terminal is coupled to the output terminal of the drive unit corresponding to the latch; the resistance value of the equivalent resistor of the latch is determined based on the circuit structure information, The first terminal of the equivalent resistor is the output terminal of the driving unit, and the second terminal is the input terminal of the latching unit; based on the resistance value of the equivalent resistor, the latching performance is determined. The embodiments of the present disclosure can accurately detect whether the latch is in a metastable state, which helps to improve the performance of the circuit.
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9.发明公开
公开(公告)号：US20240274222A1
公开(公告)日：2024-08-15
申请号：US18534495
申请日：2023-12-08
Applicant: Tektronix, Inc.
Inventor： Swapnil Jhawar , Chandra Sekhar Kappagantu , Mahesha Guttahalli Lakshmipathy , Sriram Mandyam Krishnakumar
IPC: G11C29/56
CPC classification number: G11C29/56004 , G11C29/56008 , G11C29/56016
Abstract: A test and measurement system includes a multi-stack test subsystem including a plurality of test and measurement instruments, each instrument coupled to a device under test (DUT) to receive a plurality of test signals from the DUT during a test mode of operation. One test and measurement instrument is designated as a master and the remainder are designated as extension test and measurement instruments. The master communicates control signals to each of the extensions to synchronize the test and measurement instruments to simultaneously acquire the plurality of test signals provided by the DUT. An automation engine is coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master, and the automation engine analyzes the acquired test signals to perform validation testing for each of plurality of test signals and simultaneously display results of the validation testing for the plurality of test signals.
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公开(公告)号：US12007825B2
公开(公告)日：2024-06-11
申请号：US17455219
申请日：2021-11-17
Applicant: FUJI ELECTRIC CO., LTD.
Inventor： Masashi Akahane
IPC: H04L7/00 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/3237 , G06F13/00 , G06F13/40 , H04B3/02 , B60R16/03 , G11C16/12 , G11C29/56
CPC classification number: G06F1/3237 , G06F1/04 , G06F1/10 , G06F1/12 , G06F13/00 , G06F13/40 , H04L7/00 , H04L7/0008 , H04L7/0012 , B60R16/0315 , G11C16/12 , G11C29/56012 , H04B3/02
Abstract: A slave communication apparatus including a clock recovering section that recovers a clock signal from a transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and data has a first data value, and a third signal value between the first and second signal values when the clock is the second level and the data has a second data value; and a data recovering section that recovers the data, wherein the data recovering section sets the data threshold value to be a first setting value between the second and third signal values in response to the recovered data having the second data value, and sets the data threshold value to be a second setting value between the first and third signal values in response to the recovered data having the first data value.
