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公开(公告)号：US12106816B2
公开(公告)日：2024-10-01
申请号：US17790472
申请日：2022-05-09
IPC分类号： G11C29/56
CPC分类号： G11C29/56016 , G11C29/56004
摘要： The present disclosure provide latch performance detecting method and a device. The method includes: extracting circuit structure information of a latch, having a transmission gate and a latch unit, an output terminal of the transmission gate is coupled to the input terminal of the latch unit, and the input terminal is coupled to the output terminal of the drive unit corresponding to the latch; the resistance value of the equivalent resistor of the latch is determined based on the circuit structure information, The first terminal of the equivalent resistor is the output terminal of the driving unit, and the second terminal is the input terminal of the latching unit; based on the resistance value of the equivalent resistor, the latching performance is determined. The embodiments of the present disclosure can accurately detect whether the latch is in a metastable state, which helps to improve the performance of the circuit.
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2.发明公开公开(公告)号：US20240274222A1
公开(公告)日：2024-08-15
申请号：US18534495
申请日：2023-12-08
申请人： Tektronix, Inc.
发明人： Swapnil Jhawar , Chandra Sekhar Kappagantu , Mahesha Guttahalli Lakshmipathy , Sriram Mandyam Krishnakumar
IPC分类号： G11C29/56
CPC分类号： G11C29/56004 , G11C29/56008 , G11C29/56016
摘要： A test and measurement system includes a multi-stack test subsystem including a plurality of test and measurement instruments, each instrument coupled to a device under test (DUT) to receive a plurality of test signals from the DUT during a test mode of operation. One test and measurement instrument is designated as a master and the remainder are designated as extension test and measurement instruments. The master communicates control signals to each of the extensions to synchronize the test and measurement instruments to simultaneously acquire the plurality of test signals provided by the DUT. An automation engine is coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master, and the automation engine analyzes the acquired test signals to perform validation testing for each of plurality of test signals and simultaneously display results of the validation testing for the plurality of test signals.
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公开(公告)号：US12007825B2
公开(公告)日：2024-06-11
申请号：US17455219
申请日：2021-11-17
发明人： Masashi Akahane
IPC分类号： H04L7/00 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/3237 , G06F13/00 , G06F13/40 , H04B3/02 , B60R16/03 , G11C16/12 , G11C29/56
CPC分类号： G06F1/3237 , G06F1/04 , G06F1/10 , G06F1/12 , G06F13/00 , G06F13/40 , H04L7/00 , H04L7/0008 , H04L7/0012 , B60R16/0315 , G11C16/12 , G11C29/56012 , H04B3/02
摘要： A slave communication apparatus including a clock recovering section that recovers a clock signal from a transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and data has a first data value, and a third signal value between the first and second signal values when the clock is the second level and the data has a second data value; and a data recovering section that recovers the data, wherein the data recovering section sets the data threshold value to be a first setting value between the second and third signal values in response to the recovered data having the second data value, and sets the data threshold value to be a second setting value between the first and third signal values in response to the recovered data having the first data value.
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公开(公告)号：US11961578B2
公开(公告)日：2024-04-16
申请号：US17900876
申请日：2022-09-01
发明人： Jyun-Da Chen
CPC分类号： G11C29/56008 , G06F11/1044
摘要： A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.
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公开(公告)号：US11929136B2
公开(公告)日：2024-03-12
申请号：US17906303
申请日：2021-03-18
CPC分类号： G11C29/54 , G11C29/56004
摘要： A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.
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公开(公告)号：US11879940B2
公开(公告)日：2024-01-23
申请号：US17355386
申请日：2021-06-23
发明人： Wilson Pradeep , Prakash Narayanan
IPC分类号： G01R31/3177 , G01R31/317 , G11C29/56 , G06F11/10 , G11C29/36 , G11C29/42
CPC分类号： G01R31/3177 , G01R31/31718 , G01R31/31724 , G06F11/1048 , G06F11/1068 , G11C29/36 , G11C29/42 , G11C29/56004 , G11C2029/3602 , G11C2029/5602
摘要： A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.
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公开(公告)号：US11742055B2
公开(公告)日：2023-08-29
申请号：US17984127
申请日：2022-11-09
IPC分类号： G11C29/56 , G01R31/28 , G01R31/319
CPC分类号： G11C29/56016 , G01R31/2863 , G01R31/2867 , G01R31/31905 , G11C2029/5602
摘要： A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.
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公开(公告)号：US20230012855A1
公开(公告)日：2023-01-19
申请号：US17943123
申请日：2022-09-12
发明人： Michael Sheperek , Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Larry J. Koudele
摘要： A method can include receiving a request to read data from a block of a memory device, identifying a block family associated with the block of the memory device, identifying a voltage distribution parameter value associated with the block family, wherein the voltage distribution parameter value reflects an aggregate value of a corresponding voltage distribution associated with a plurality of memory cells of the block family, and determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device. The block family can be identified using a data structure that maps block identifiers to corresponding block family identifiers. The voltage distribution parameter value can be identified using a data structure that maps block family identifiers to corresponding voltage parameter values.
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公开(公告)号：US11501846B2
公开(公告)日：2022-11-15
申请号：US17239651
申请日：2021-04-25
发明人： Sanglok Kim , Youngdon Choi
IPC分类号： G11C29/56
摘要： A semiconductor memory device included in each of a plurality of chips which are divided by a scribe lane and formed on an upper surface of a wafer, includes a memory core and a built-in self test (BIST) circuit. The memory core includes a memory cell array that stores data and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.
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公开(公告)号：US11443830B1
公开(公告)日：2022-09-13
申请号：US17217780
申请日：2021-03-30
摘要： A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a first data structure mapping block identifiers to corresponding block family identifiers, a block family associated with the block of the memory device, determining, using a second data structure mapping block family identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block family, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device, and reading, using the determined set of read levels, data from the block of the memory device.
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