公开(公告)号：US20240292502A1

公开(公告)日：2024-08-29

申请号：US18659170

申请日：2024-05-09

申请人： Lutron Technology Company LLC

发明人： Russell Weightman ,  Jonathan T. Lenz ,  Jaykrishna A. Shukla ,  Daniel Curtis Raneri

IPC分类号： H05B39/08 ,  G11C5/00 ,  G11C5/02 ,  G11C7/04 ,  G11C7/24 ,  G11C11/406 ,  G11C29/12 ,  H05B39/04 ,  H05B47/10 ,  H05B47/165 ,  H05B47/17 ,  H05B47/185

CPC分类号： H05B39/086 ,  G11C5/005 ,  G11C5/025 ,  G11C7/04 ,  G11C7/24 ,  G11C11/40626 ,  G11C29/12 ,  H05B39/04 ,  H05B47/10 ,  H05B47/165 ,  H05B47/17 ,  H05B47/185

摘要： A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.

公开(公告)号：US11778748B2

公开(公告)日：2023-10-03

申请号：US17180067

申请日：2021-02-19

申请人： Western Digital Technologies, Inc.

发明人： Uthayarajan A/L Rasalingam ,  Go Beng Siong

IPC分类号： H05K1/18 ,  G11C5/00 ,  H05K1/00 ,  H05K1/14

CPC分类号： H05K1/189 ,  G11C5/00 ,  H05K1/00 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/05 ,  H05K2201/10159

摘要： A data storage device including a first printed circuit board (PCB) and a second PCB. The first PCB includes a controller, an interface configured to interface with a host device, and a first connector. The second PCB includes a non-volatile memory and a second connector. The second connector is configured to couple to the first connector to establish a communication connection between the controller and the non-volatile memory.

公开(公告)号：US20230206959A1

公开(公告)日：2023-06-29

申请号：US18114692

申请日：2023-02-27

申请人： Micron Technology, Inc.

发明人： Marcello Mariani ,  Antonino Rigano

IPC分类号： G11C5/00 ,  G11C5/06 ,  G11C5/02 ,  H10B12/00

CPC分类号： G11C5/005 ,  G11C5/025 ,  G11C5/063 ,  H10B12/315

摘要： Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

公开(公告)号：US11558939B2

公开(公告)日：2023-01-17

申请号：US17402809

申请日：2021-08-16

申请人： Lutron Technology Company LLC

发明人： Russell Weightman ,  Jonathan T. Lenz ,  Jaykrishna A. Shukla ,  Daniel Curtis Raneri

IPC分类号： H05B39/08 ,  G11C5/00 ,  G11C5/02 ,  G11C11/406 ,  H05B47/185 ,  H05B47/165 ,  H05B47/17 ,  H05B47/10 ,  H05B39/04 ,  G11C7/04 ,  G11C7/24 ,  G11C29/12

摘要： A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source.

公开(公告)号：US11450354B2

公开(公告)日：2022-09-20

申请号：US17340681

申请日：2021-06-07

申请人： Micron Technology, Inc.

发明人： Joe M. Jeddeloh ,  Brent Keeth

IPC分类号： G11C5/00 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02 ,  H01L25/18 ,  G11C11/4063

摘要： Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

公开(公告)号：US11379366B2

公开(公告)日：2022-07-05

申请号：US17098491

申请日：2020-11-16

申请人： MICRON TECHNOLOGY, INC.

发明人： Terry Grunzke

IPC分类号： G06F12/06 ,  H04L25/02 ,  G11C16/06 ,  G11C5/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G06F13/18 ,  G06F13/16

摘要： Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.

公开(公告)号：US11327113B2

公开(公告)日：2022-05-10

申请号：US16525077

申请日：2019-07-29

申请人： Micron Technology, Inc.

发明人： David D. Wilmoth

IPC分类号： G01R31/317 ,  G06F11/30 ,  G01R31/3185 ,  G11C7/10 ,  G11C29/48 ,  G11C11/401 ,  G11C29/02 ,  G11C5/04 ,  G11C5/00 ,  G11C29/12 ,  G06F9/38 ,  G11C7/22 ,  G11C29/04

摘要： One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

公开(公告)号：US11295785B2

公开(公告)日：2022-04-05

申请号：US16877752

申请日：2020-05-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Woosung Lee ,  Chunghyun Ryu ,  Hyoungtaek Lim

IPC分类号： G11C5/00 ,  G11C5/14

摘要： A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

公开(公告)号：USRE48997E1

公开(公告)日：2022-03-29

申请号：US16452252

申请日：2019-06-25

申请人： KIOXIA CORPORATION

发明人： Akihisa Fujimoto ,  Hiroyuki Sakamoto

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G06F9/30 ,  G11C5/00

摘要： According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

公开(公告)号：US11061614B2

公开(公告)日：2021-07-13

申请号：US16658444

申请日：2019-10-21

申请人： SK hynix Inc.

发明人： Chui Sung Kang

IPC分类号： G06F3/06 ,  G11C5/00 ,  G11C7/10

摘要： An electronic apparatus includes a storage device having a plurality of memory blocks including a first memory block; and a controller configured to control the storage device to perform a read operation for the first memory block in response to a read request of a host. The controller controls the storage device to perform a refresh operation for the first memory block based on whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block when performing the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block.