公开(公告)号：US20250069630A1

公开(公告)日：2025-02-27

申请号：US18545370

申请日：2023-12-19

Applicant: SK hynix Inc.

Inventor： Hyung Sik WON ,  Seung Hwan KIM ,  Jun Ho CHEON

IPC: G11C7/18 ,  G11C5/06

Abstract: A semiconductor device may include a bit line extending in a third direction, a plurality of active layers extending in a first direction and contacting the bit line, a plurality of word lines extending in a second direction and each disposed at an top surface or bottom surface of each of the plurality of active layers, a plurality of capacitors contacting the plurality of active layers, and a contact formed in at least one active layer disposed at the uppermost part of the bit line, among the plurality of active layers. The bit line and the contact may be electrically connected or separated by using, as a control line, a word line disposed in the top surface or bottom surface of the at least one active layer, among the plurality of word lines.

公开(公告)号：US12237287B2

公开(公告)日：2025-02-25

申请号：US18369115

申请日：2023-09-15

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Kenneth Ma ,  Balakrishna Jayadev ,  Sagheer Ahmad

IPC: G11C5/00 ,  G11C5/06 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US12232321B2

公开(公告)日：2025-02-18

申请号：US18475335

申请日：2023-09-27

Applicant: KIOXIA CORPORATION

Inventor： Go Oike ,  Tsuyoshi Sugisaki

IPC: H10B41/00 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L29/792

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

公开(公告)号：US12218056B2

公开(公告)日：2025-02-04

申请号：US17018812

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Christopher Kinney

IPC: H01L23/528 ,  G11C5/06 ,  H01L23/522

Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).

公开(公告)号：US12217817B2

公开(公告)日：2025-02-04

申请号：US18356204

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Piao Chiu ,  Yu-Sheng Chen

IPC: G11C5/06 ,  H01L25/065 ,  H10B63/10 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

Abstract: A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

公开(公告)号：US20250037746A1

公开(公告)日：2025-01-30

申请号：US18680395

申请日：2024-05-31

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C7/22 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02

Abstract: A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.

公开(公告)号：US20250037743A1

公开(公告)日：2025-01-30

申请号：US18401945

申请日：2024-01-02

Applicant: SK hynix Inc.

Inventor： Nam Jae LEE

IPC: G11C5/06 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40

Abstract: A memory device, and a method of manufacturing the memory device, includes a lower structure including a first pad exposed through a top surface of the lower structure. The memory device also includes an upper structure including a second pad exposed through a bottom surface of the upper structure. The first and second pads are bonded to each other, and an interface at which the first and second pads are bonded to each other forms a curved surface.

公开(公告)号：US12213312B2

公开(公告)日：2025-01-28

申请号：US18305685

申请日：2023-04-24

Applicant: Kioxia Corporation

Inventor： Kaihei Kato ,  Takashi Fukushima ,  Kazutaka Suzuki

IPC: H10B43/50 ,  G11C5/02 ,  G11C5/06 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device includes a substrate having a surface, a first conductive layer 25 disposed on a substrate and extending in an X direction parallel to the surface of the substrate; a second conductive layer 25 that disposed on the first conductive layer 25 and extending in the X direction; an insulation plug 30 disposed on the substrate, extends in a Z direction intersecting with the X direction, and intersects with the first conductive layer 25; and a contact plug CC disposed on the first insulation plug 30, extends in the Z direction, and intersects with the second conductive layer 25.

公开(公告)号：US12211538B2

公开(公告)日：2025-01-28

申请号：US18203877

申请日：2023-05-31

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani ,  Agostino Pirovano

IPC: G11C11/22 ,  G11C5/06 ,  H01L29/51 ,  H10B53/10 ,  H10B53/20

Abstract: Methods, systems, and devices for techniques to manufacture ferroelectric memory devices are described. In some cases, a memory array may be manufactured using a self-aligned manufacturing technique. For example, a continuous layer of dielectric material may be formed over an assembly which includes an array of transistors coupling contacts on the surface of the assembly with a set of digit lines. In some cases, an array of cavities may be etched into the dielectric material, each cavity exposing a set of contacts. A set of bottom electrodes corresponding to the set of contacts may be formed on sidewalls in each cavity, for example by depositing a layer of electrode material and etching the electrode material using a variety of hard masks.

公开(公告)号：US20250024685A1

公开(公告)日：2025-01-16

申请号：US18755360

申请日：2024-06-26

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Jie Zhou ,  Christopher J. Petti ,  Eli Harari ,  Kavita Shah

IPC: H10B51/20 ,  G11C5/06 ,  G11C16/04 ,  G11C16/14 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10

Abstract: A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.