公开(公告)号：US12082399B2

公开(公告)日：2024-09-03

申请号：US17539760

申请日：2021-12-01

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Dongxue Zhao ,  Tao Yang ,  Yuancheng Yang ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H10B12/00 ,  G11C5/10 ,  G11C11/22 ,  G11C11/402 ,  H10B53/20

CPC分类号： H10B12/37 ,  G11C5/10 ,  G11C11/221 ,  G11C11/4023 ,  H10B53/20

摘要： In certain aspects, a memory device includes an array of memory cells, a plurality of word lines, and a plurality of slit structures. Each memory cell includes a vertical transistor, and a storage unit coupled to the vertical transistor. The array of memory cells is arranged in rows in a first direction and columns in a second direction. Two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view. Each word line extends in the second direction. Each slit structure extends in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction.

公开(公告)号：US20240087616A1

公开(公告)日：2024-03-14

申请号：US18463686

申请日：2023-09-08

申请人： Kioxia Corporation

发明人： Takafumi MASUDA ,  Nobuyoshi SAITO ,  Mutsumi OKAJIMA ,  Keiji IKEDA

IPC分类号： G11C5/06 ,  G11C5/10

CPC分类号： G11C5/063 ,  G11C5/10

摘要： A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.

公开(公告)号：US20240038280A1

公开(公告)日：2024-02-01

申请号：US18184792

申请日：2023-03-16

申请人： Kioxia Corporation

发明人： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC分类号： G11C5/10 ,  G11C11/4097 ,  G11C11/4096

CPC分类号： G11C5/10 ,  G11C11/4097 ,  G11C11/4096

摘要： A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.

公开(公告)号：US20230253315A1

公开(公告)日：2023-08-10

申请号：US18133575

申请日：2023-04-12

申请人： Samsung Electronics Co., Ltd.

发明人： TAEJIN PARK ,  KEUNNAM KIM ,  SOHYUN PARK ,  JIN-HWAN CHUN ,  WOOYOUNG CHOI ,  SUNGHEE HAN ,  INKYOUNG HEO ,  YOOSANG HWANG

IPC分类号： H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L21/768 ,  H10B12/00

CPC分类号： H01L23/528 ,  H01L29/0649 ,  G11C5/10 ,  H01L29/4236 ,  H01L21/76831 ,  H10B12/485

摘要： The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20230134556A1

公开(公告)日：2023-05-04

申请号：US17539802

申请日：2021-12-01

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L27/11514 ,  H01L27/108 ,  G11C5/02 ,  G11C11/402 ,  G11C11/22 ,  G11C5/10

摘要： In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

公开(公告)号：US20230081882A1

公开(公告)日：2023-03-16

申请号：US17474689

申请日：2021-09-14

申请人： Intel Corporation

发明人： Sean T. Ma ,  Abhishek A. Sharma ,  Aaron D. Lilak ,  Hui Jae Yoo ,  Scott B. Clendenning ,  Van H. Le ,  Tristan A. Tronic ,  Urusa Alaan

IPC分类号： H01L27/108 ,  H01L27/06 ,  G11C5/10

摘要： A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

公开(公告)号：US11482525B2

公开(公告)日：2022-10-25

申请号：US17129063

申请日：2020-12-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chih-Hung Chen

IPC分类号： H01L27/108 ,  G11C5/10

摘要： The present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; limning a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.

公开(公告)号：US20220199623A1

公开(公告)日：2022-06-23

申请号：US17129063

申请日：2020-12-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chih-Hung CHEN

IPC分类号： H01L27/108 ,  G11C5/10

摘要： The present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; limning a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.

公开(公告)号：US11282548B1

公开(公告)日：2022-03-22

申请号：US17307686

申请日：2021-05-04

申请人： Micron Technology, Inc.

发明人： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC分类号： G11C5/10 ,  H01L27/108 ,  H01L49/02 ,  G11C11/405 ,  H01L27/06

摘要： Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210375876A1

公开(公告)日：2021-12-02

申请号：US17402723

申请日：2021-08-16

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Yasuhiko TAKEMURA

IPC分类号： H01L27/108 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L49/02 ,  G11C5/10 ,  G11C11/401 ,  H01L29/786 ,  G11C11/408 ,  H01L23/528 ,  H01L23/532

摘要： The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.