公开(公告)号：US12154658B2

公开(公告)日：2024-11-26

申请号：US17941719

申请日：2022-09-09

Applicant: SK hynix Inc.

Inventor： Kwang Soon Kim

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/04 ,  G11C8/10 ,  H03K19/20

Abstract: A semiconductor device includes: a memory cell array including a plurality of memory cells; a data input/output circuit suitable for outputting data provided from the memory cell array in response to a couple of data output control signals; and a data output control circuit suitable for generating a couple of latch read enable signals and a couple of data output control timing signals based on a couple of complementary read enable signals, an internal enable signal and warming-up cycle information indicating different warming-up cycles, and outputting, according to the couple of data output control timing signals, the couple of data output control signals using the couple of latch read enable signals, one or more pulses of each of which are masked according to the warming-up cycle information.

公开(公告)号：US12094555B2

公开(公告)日：2024-09-17

申请号：US17884963

申请日：2022-08-10

Applicant: SK hynix Inc.

Inventor： Jae Hyung Park ,  Seung Geun Baek ,  Dong Uk Lee

IPC: G11C5/00 ,  G11C5/02 ,  G11C8/10 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C5/02 ,  G11C8/10 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.

公开(公告)号：US12068031B2

公开(公告)日：2024-08-20

申请号：US17901239

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Jun Deguchi ,  Daisuke Miyashita ,  Atsushi Kawasumi ,  Hidehiro Shiga ,  Shinji Miyano ,  Shinichi Sasaki

IPC: G11C16/08 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

公开(公告)号：US12062393B2

公开(公告)日：2024-08-13

申请号：US17471597

申请日：2021-09-10

Applicant: KIOXIA CORPORATION

Inventor： Gou Fukano

IPC: G11C16/04 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08 ,  G11C16/16 ,  H10B43/27 ,  H10B43/40

CPC classification number: G11C16/0483 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08 ,  G11C16/16 ,  H10B43/27 ,  H10B43/40

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

公开(公告)号：US20240237364A1

公开(公告)日：2024-07-11

申请号：US18417830

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC: H10B99/00 ,  G11C8/10 ,  G11C8/12 ,  H01L21/027 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/20 ,  H10B53/40 ,  H10B63/00

CPC classification number: H10B99/00 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78696 ,  G11C8/10 ,  G11C8/12 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H10B53/20 ,  H10B53/40 ,  H10B63/84

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

公开(公告)号：US12027204B2

公开(公告)日：2024-07-02

申请号：US18357785

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

公开(公告)号：US11996161B2

公开(公告)日：2024-05-28

申请号：US17805270

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C7/1084 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1087 ,  G11C8/10 ,  G11C8/18

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

公开(公告)号：US20240170032A1

公开(公告)日：2024-05-23

申请号：US18389314

申请日：2023-11-14

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1069 ,  G11C8/10

Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location in response to assertion of control signal having a dynamically variable delay dependent on the current data word. The operations are advantageously performed within a single clock cycle.

公开(公告)号：US20240127875A1

公开(公告)日：2024-04-18

申请号：US18474406

申请日：2023-09-26

Applicant: EM Microelectronic-Marin SA

Inventor： Lubomir PLAVEC ,  Yves GODAT

IPC: G11C8/10

CPC classification number: G11C8/10 ,  H03K19/20

Abstract: An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).

公开(公告)号：US11915783B2

公开(公告)日：2024-02-27

申请号：US17695613

申请日：2022-03-15

Applicant: SK hynix Inc.

Inventor： Gi Moon Hong ,  Dong Yoon Ka

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10

CPC classification number: G11C7/1069 ,  G11C7/22 ,  G11C8/10

Abstract: A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.