公开(公告)号：US20240394177A1

公开(公告)日：2024-11-28

申请号：US18675127

申请日：2024-05-27

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh Bhakta

IPC: G06F12/00 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12

Abstract: A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. A respective data buffer includes data paths and logic configurable to, in response to the second module control signals, enable at least a subset of the data paths to receive and regenerate signals carrying a section of the data communicated from/to corresponding module data lines. The logic is further configurable to disable the data paths when the memory module is not communicating data with the memory controller.

公开(公告)号：US20240386983A1

公开(公告)日：2024-11-21

申请号：US18671201

申请日：2024-05-22

Applicant: Lodestar Licensing Group LLC

Inventor： Keisuke Fujishiro ,  Yoshifumi Mochida

IPC: G11C29/42 ,  G11C7/10 ,  G11C8/12

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.

公开(公告)号：US20240331759A1

公开(公告)日：2024-10-03

申请号：US18594666

申请日：2024-03-04

Applicant: Lodestar Licensing Group LLC

Inventor： Alberto Troia

IPC: G11C11/409 ,  G06F9/30 ,  G06N3/04 ,  G06N3/06 ,  G11C8/12 ,  G11C11/4074

CPC classification number: G11C11/409 ,  G06F9/30101 ,  G06N3/04 ,  G06N3/06 ,  G11C8/12 ,  G11C11/4074

Abstract: The present disclosure includes apparatuses and methods related to an artificial intelligence accelerator in memory. An example apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

公开(公告)号：US20240331752A1

公开(公告)日：2024-10-03

申请号：US18737111

申请日：2024-06-07

Applicant: SK hynix Inc.

Inventor： Ki Hun KWON ,  Jae Il KIM

IPC: G11C7/22 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C5/063 ,  G11C8/12

Abstract: A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.

公开(公告)号：US20240321331A1

公开(公告)日：2024-09-26

申请号：US18737192

申请日：2024-06-07

Applicant: SK hynix Inc.

Inventor： Jae Il KIM

IPC: G11C7/22 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C5/063 ,  G11C8/12

Abstract: A semiconductor device includes a first rank and a second rank. The first rank operates in synchronization with a clock signal in response to a first rank selection signal, and the second rank operates in synchronization with the clock signal in response to a second rank selection signal. The first rank performs a termination operation without performing an internal control operation if the first rank selection signal maintains an enabled state in synchronization with a first edge and a second edge of the clock signal.

公开(公告)号：US12099453B2

公开(公告)日：2024-09-24

申请号：US17709031

申请日：2022-03-30

Applicant: NVIDIA Corporation

Inventor： William James Dally ,  Carl Thomas Gray ,  Stephen W. Keckler ,  James Michael O'Connor

IPC: G06F13/16 ,  G11C8/12 ,  H03K19/1776

CPC classification number: G06F13/161 ,  G06F13/1673 ,  G06F13/1689 ,  G11C8/12 ,  H03K19/1776

Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

公开(公告)号：US12087347B2

公开(公告)日：2024-09-10

申请号：US18353776

申请日：2023-07-17

Applicant: Lodestar Licensing Group, LLC

Inventor： Joo-Sang Lee

IPC: G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4087

Abstract: Methods of operating a memory device are disclosed. A method may include determining an amount of activity associated with at least one memory bank of a memory device. The method may further include adjusting a row hammer refresh rate for the at least one memory bank based on the amount of activity associated with the at least one memory bank. Memory devices and systems are also described.

公开(公告)号：US12066948B2

公开(公告)日：2024-08-20

申请号：US17699401

申请日：2022-03-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0877 ,  G11C7/10 ,  G11C8/12

CPC classification number: G06F12/0877 ,  G06F12/0246 ,  G06F12/0661 ,  G11C7/1045 ,  G11C8/12

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

公开(公告)号：US12014789B2

公开(公告)日：2024-06-18

申请号：US17813079

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Keisuke Fujishiro ,  Yoshifumi Mochida

IPC: G11C29/00 ,  G11C7/10 ,  G11C8/12 ,  G11C29/42

CPC classification number: G11C29/42 ,  G11C7/106 ,  G11C7/109 ,  G11C8/12

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.

公开(公告)号：US11810620B2

公开(公告)日：2023-11-07

申请号：US17458067

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki Takenaka ,  Akihiko Chiba ,  Teppei Higashitsuji ,  Kiyofumi Sakurai ,  Hiroaki Nakasa ,  Youichi Magome

IPC: G11C8/12 ,  G11C16/14 ,  G11C5/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/30 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.