公开(公告)号：US3906544A

公开(公告)日：1975-09-16

申请号：US46292474

申请日：1974-04-22

申请人： GEN ELECTRIC

发明人： ENGELER WILLIAM E ,  TIEMANN JEROME J

IPC分类号： H01L27/108 ,  H01L27/148 ,  H01L11/14

CPC分类号： H01L27/108 ,  H01L27/14831

摘要： A radiation responsive semiconductor imaging device comprising an array of charge storage devices arranged in rows and columns on the surface of a semiconductor substrate. Each storage device includes a conductor-insulator-semiconductor structure in which minority carriers, controllably generated within the semiconductor in proportional response to incident electromagnetic radiation flux, are stored at the surface of the semiconductor beneath the conductor due to the application of a depletion region forming voltage to the conductor. Means are disclosed for transferring the integrated electrical charge from the storage region to a receiver region for electrical readout of the stored information. Means for reading out selected electrical charges while continuing to store other electrical charges are also disclosed. Means are also disclosed for altering the sensitivity of the array without a sacrifice in dynamic range.

摘要翻译： 一种辐射响应半导体成像装置，包括在半导体衬底的表面上以行和列布置的电荷存储装置的阵列。 每个存储装置包括导体 - 绝缘体 - 半导体结构，其中由半导体中可控地产生的少数载流子与入射电磁辐射通量成正比地存储在导体下方的半导体表面处，这是由于施加耗尽区形成 导体电压。 公开了用于将积分电荷从存储区域传送到接收器区域以便电存储信息的装置。 还公开了在继续存储其他电荷的同时读取所选择的电荷的装置。 还公开了用于在动态范围内没有牺牲的情况下改变阵列的灵敏度的手段。

公开(公告)号：US3886583A

公开(公告)日：1975-05-27

申请号：US40898473

申请日：1973-10-23

申请人： MOTOROLA INC

发明人： WANG RAYMOND C

IPC分类号： H01L21/00 ,  H01L27/092 ,  H01L29/00 ,  H01L11/14

CPC分类号： H01L21/00 ,  H01L27/0927 ,  H01L29/00

摘要： There is disclosed an improved insulated gate field-effect transistor having a reduced gate voltage associated with the use of an aluminum-silicon gate electrode in which the electrode is composed of 90% aluminum and 10% silicon by weight. The use of the aluminum-silicon electrode in the weight percentages indicated permits the fabrication of complementary insulated gate field-effect transistors, both of which having as low a gate voltage as that of a corresponding ''''silicon gate'''' device without the inherent processing problems and reliability difficulties of the silicon gate devices. The improved complementary insulated gate field-effect transistor device is made by standard C-MOS processing techniques with the major difference in processing being the co-evaporation of aluminum and silicon during the gate electrode deposition in lieu of evaporation of pure aluminum.

公开(公告)号：US3877055A

公开(公告)日：1975-04-08

申请号：US46039174

申请日：1974-04-12

申请人： MOTOROLA INC

发明人： FISHER JOHN ANDREW ,  POWELL MICHAEL WILLIAM

IPC分类号： G11C16/04 ,  H01L27/088 ,  H01L29/792 ,  H01L11/14

CPC分类号： G11C16/0466 ,  H01L27/088 ,  H01L29/792

摘要： A fixed threshold MNOS device and a variable threshold MNOS device internally connected in series with a diffused area in the substrate, having a conductivity type opposite that of the substrate, in contact with both of the devices to provide a common source-drain. The diffused area forming the common sourcedrain is added to remove variations in channel length in the devices.

公开(公告)号：US3875656A

公开(公告)日：1975-04-08

申请号：US38262673

申请日：1973-07-25

申请人： MOTOROLA INC

发明人： HANDY ROBERT M

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/86 ,  H01L23/482 ,  H01L27/115 ,  H01L27/12 ,  H01L29/00 ,  H01L29/788 ,  H01L29/792 ,  H01L11/14

CPC分类号： H01L29/792 ,  H01L21/86 ,  H01L23/4825 ,  H01L27/115 ,  H01L27/12 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an array of high density single fieldeffect transistor, electrically alterable memory devices, wherein no ohmic contacts are required within the array and self-aligning devices are provided. A plurality of substantially vertical parallel elongated regions of silicon are provided on an insulating substrate, each elongated region having a plurality of openings therein. The plurality of rectangular silicon nitridesilicon dioxide composite gate insulator regions are provided on the elongated silicon regions, each composite insulator region extending between two of said openings. The silicon nitride insulator regions act as diffusion masks and also as oxidation masks during subsequent diffusion and thermal oxidation steps. A plurality of substantially horizontal parallel metal regions are provided on the exposed surface, each acting as the gate electrode for all of the electrically alterable memory devices in a given row.

公开(公告)号：US3872359A

公开(公告)日：1975-03-18

申请号：US13984171

申请日：1971-05-03

申请人： FEUERSANGER A

发明人： FEUERSANGER A

IPC分类号： C23C14/08 ,  H01L29/49 ,  H01L29/786 ,  H01L11/14

CPC分类号： H01L29/78681 ,  C23C14/085 ,  H01L29/4908

摘要： A thin film transistor utilizing an insulated gate structure is described wherein the semiconducting layer is formed of defectnickel oxide having the general formula Ni(1 x)O, wherein x is within the range of 10 7 to 10 2. In a preferred embodiment, the insulating layer overlying the defect-nickel oxide semiconducting layer is formed of stoichiometric nickel oxide thereby reducing the number of steps required in fabrication. The thin film transistor is fabricated within a single system by utilizing reactive sputtering for the formation of the semiconducting and insulating layers. The sputtering takes place in a pure oxygen atmosphere in the absence of inert gases with the result that the characteristics of the deposited nickel oxide films can be varied by controlling the deposition rate during sputtering.

公开(公告)号：US3868187A

公开(公告)日：1975-02-25

申请号：US28522572

申请日：1972-08-31

申请人： TOKYO SHIBAURA ELECTRIC CO

发明人： MASUOKA FUJIO

IPC分类号： H01L29/00 ,  H01L29/788 ,  H01L11/14

CPC分类号： H01L29/7886 ,  H01L29/00

摘要： Avalanche injection type MOS memory having a floating gate surrounded by an insulating layer between the source and drain regions formed on one side of a semiconductor substrate wherein there is formed one or two auxiliary semiconductor regions with the same type of conductivity as, but with higher concentrations of impurities than, said semiconductor substrate in the channel region thereof defined between said source and drain regions so as to contact either of these regions.

摘要翻译： 雪崩注入型MOS存储器，其具有由在半导体衬底的一侧上形成的源极和漏极区域之间的绝缘层包围的浮置栅极，其中形成一个或两个具有相同类型的导电性但具有较高浓度的辅助半导体区域 的杂质，其沟道区中的所述半导体衬底限定在所述源极和漏极区之间，以便接触这些区域中的任一个。

公开(公告)号：US3806772A

公开(公告)日：1974-04-23

申请号：US22404572

申请日：1972-02-07

申请人： FAIRCHILD CAMERA INSTR CO

发明人： EARLY J

IPC分类号： H01L29/768 ,  H03F1/18 ,  H01L11/14

CPC分类号： H01L29/76816 ,  H03F1/18

摘要： A charge coupled distributed amplifier comprises a first plurality of charge storage wells arranged along a first selected line, a second plurality of charge storage wells arranged along a second selected line, and a multiplicity of amplifier means, each amplifier means electrically coupling one charge storage well in the first plurality of wells to a corresponding charge storage well in the second plurality of wells. Charges are driven along the first and second pluralities of charge storage wells in synchronization. The same charge in the first plurality of charge storage wells creates an additional increment of charge in each charge storage well connected to the output of each amplifier means which adds in that well to the previously accumulated charge in the second plurality of charge storage wells. Thus a given amount of input charge is amplified coherently to produce a detectable output signal.

摘要翻译： 电荷耦合分布放大器包括沿着第一选定线布置的第一多个电荷存储阱，沿着第二选定线布置的第二多个电荷存储阱和多个放大器装置，每个放大器装置电耦合一个电荷存储阱 在第一组多个孔中，在第二个多个孔中与相应的电荷存储阱相对。 同步沿着第一和第二多个电荷存储阱驱动电荷。 在第一多个电荷存储阱中的相同电荷在每个电荷存储阱中产生附加的电荷增量，其连接到每个放大器装置的输出，该放大器装置将该阱中的第二个多个电荷存储阱中的先前累积的电荷相加。 因此，给定量的输入电荷被相干地放大以产生可检测的输出信号。

公开(公告)号：US3805130A

公开(公告)日：1974-04-16

申请号：US37615473

申请日：1973-07-03

申请人： YAMAZAKI S

发明人： YAMAZAKI S

IPC分类号： H01L29/788 ,  H01L11/14

CPC分类号： H01L29/7881

摘要： A semiconductor device is disclosed having a layer of metal clusters or semiconductor clusters acting as trap centers for electrons or holes to control the electrical properties of the device.

摘要翻译： 公开了一种半导体器件，其具有作为用于电子或空穴的阱中心的金属簇或半导体簇的层，以控制器件的电性能。

公开(公告)号：US3796932A

公开(公告)日：1974-03-12

申请号：US3796932D

申请日：1971-06-28

申请人： BELL TELEPHONE LABOR INC

发明人： AMELIO G ,  KRAMBECK R ,  PICKAR K

IPC分类号： G11C19/28 ,  H01L29/10 ,  H01L29/768 ,  H01L11/14

CPC分类号： H01L29/1062 ,  G11C19/282 ,  H01L29/76833 ,  H01L29/76841 ,  H01L29/76866

摘要： In Charge Coupled Apparatus laterally graded distributions of immobile charge are disposed under the electrodes and, optionally, between the electrodes to enhance the desired unidirectionality of charge transfer and, optionally, to enable the gap regions between electrodes to act as active storage sites in the information channel. A graded distribution of immobile charge under an electrode provides a built-in electric field in the desired direction of charge propagation so that fieldenhanced charge transfer, and concomitant improved speed, is effected. A graded distribution of immobile charge in a gap between electrodes provides a built-in, suitably asymmetric potential well in the gap. This built-in potential well in the gap can be used as a temporary storage site for charge carriers (much like any other potential well in a CCD) to enable one-phase operation and more compact devices.

公开(公告)号：US3796927A

公开(公告)日：1974-03-12

申请号：US3796927D

申请日：1970-12-16

申请人： BELL TELEPHONE LABOR INC

发明人： BOYLE W ,  SMITH G

IPC分类号： G11C11/35 ,  G11C19/28 ,  H01L29/10 ,  H01L29/768 ,  H03K17/56 ,  H04Q3/52 ,  H01L11/14

CPC分类号： G11C11/35 ,  G11C19/282 ,  G11C19/287 ,  H01L29/1091 ,  H01L29/768 ,  H03K17/56 ,  H04Q3/521

摘要： The specification describes a new class of semiconductor devices in which the charge is controllably translated in three dimensions. Translation control circuits can be disposed on both sides of the usual semiconductor wafer giving a new dimension in the design of logic and memory devices. In the exemplary specific embodiment the concept is described in connection with a shift register. Extension to logic circuits, e.g., to perform crossover and fan-in functions, is straightforward.