公开(公告)号：US20250068086A1

公开(公告)日：2025-02-27

申请号：US18813454

申请日：2024-08-23

Applicant: Qatar Foundation for Education, Science and Community Development

Inventor： Hicham Hamoudi ,  Sara Iyad Mohd Saleh Ahmad

IPC: G03F7/00 ,  B33Y40/20 ,  B33Y70/10 ,  B33Y80/00 ,  G03F7/20 ,  H01L21/04

Abstract: A maskless photolithography technique is provided for the direct synthesis and integration of metallic nanostructures exhibiting branching and flower-like fractal geometries on two-dimensional (2D) carbon-based nanosheets, employing room temperature ultraviolet (UV) irradiation. The photolithography process leverages the structural and electronic properties of carbon-based nanosheets comprising semiconducting organic carbon-based molecular monolayers connected by metallic atoms providing strong covalent linkages. By embedding the metallic precursor for fractal nanostructures within the carbon-based nanosheet during the initial synthesis, UV irradiation initiates the photoreduction of metallic atoms and their growth into fractal nanostructures with high yield and uniformity.

公开(公告)号：US12230704B2

公开(公告)日：2025-02-18

申请号：US16984123

申请日：2020-08-03

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yasuyuki Hoshi

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/04 ,  H01L23/49 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.

公开(公告)号：US12230693B2

公开(公告)日：2025-02-18

申请号：US17765295

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong He ,  Sen Zhang

IPC: H01L21/00 ,  H01L21/04 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.

公开(公告)号：US20250040197A1

公开(公告)日：2025-01-30

申请号：US18713872

申请日：2022-12-06

Applicant: THE RESEARCH FOUNDATION FOR THE STATE UNIVERSTIY OF NEW YORK

Inventor： Woongje SUNG

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A field effect transistor includes first section and second sections. The first section includes a drift layer. A first P-well is disposed over the drift layer. A first N-source is disposed over the first P-well. A first channel is disposed in an upper portion of the first P-well. The second section includes an area P-well disposed within the drift layer and formed integral with the first P-well. The area P-well includes sidewalls that extend upwards from the drift layer to form an enclosed structure with an outer perimeter and an inner perimeter. An area N-source surrounds the outer perimeter and is formed integral with the first N-source. An upwardly extending intermediate portion of the drift layer extends upwards though the inner perimeter. A second channel is disposed in an upper portion of the sidewalls and is bounded by the inner perimeter and outer perimeter of the sidewalls.

公开(公告)号：US12211902B2

公开(公告)日：2025-01-28

申请号：US17520882

申请日：2021-11-08

Applicant: DENSO CORPORATION

Inventor： Masato Noborio ,  Takehiro Kato ,  Yusuke Yamashita

IPC: H01L29/10 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

公开(公告)号：US20250031428A1

公开(公告)日：2025-01-23

申请号：US18905287

申请日：2024-10-03

Applicant: ROHM CO., LTD.

Inventor： Seiya NAKAZAWA ,  Sawa HARUYAMA

IPC: H01L29/417 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872

Abstract: A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.

公开(公告)号：US12198978B2

公开(公告)日：2025-01-14

申请号：US17820049

申请日：2022-08-16

Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

Inventor： Shouhei Kitajima ,  Ryo Kasai

IPC: H01L21/768 ,  H01L21/04 ,  H01L21/308

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor layer on an upper surface of a substrate, forming an etching stopper on an upper surface of the semiconductor layer, forming a metal mask including a seed film and a plating film on a lower surface of the substrate, the metal mas having an opening inside the etching stopper in plan view, forming a through-hole in the substrate and the semiconductor layer from the lower surface of the substrate to the etching stopper through the opening, and removing the plating film by an anodic reaction in an electrolyte solution after forming the through-hole.

公开(公告)号：US12176396B2

公开(公告)日：2024-12-24

申请号：US18076774

申请日：2022-12-07

Applicant: Infineon Technologies AG

Inventor： Michael Hell ,  Rudolf Elpelt ,  Thomas Ganner ,  Caspar Leendertz

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a silicon carbide semiconductor body. A first shielding region of a first conductivity type is connected to a first contact at a first surface of the silicon carbide semiconductor body. A current spread region of a second conductivity type is connected to a second contact at a second surface of the silicon carbide semiconductor body. A doping concentration profile of the current spread region includes peaks along a vertical direction perpendicular to the first surface. A doping concentration of one peak or one peak-group of the peaks is at least 50% higher than a doping concentration of any other peak of the current spread region. A vertical distance between the one peak or the one peak-group of the current spread region and the first surface is larger than a second vertical distance between the first surface and a maximum doping peak of the first shielding region.

公开(公告)号：US20240413197A1

公开(公告)日：2024-12-12

申请号：US18813208

申请日：2024-08-23

Applicant: Wolfspeed, Inc.

Inventor： Daniel J. Lichtenwalner ,  Naeem Islam ,  Woongsun Kim ,  Sei-Hyung Ryu

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns.

公开(公告)号：US20240395905A1

公开(公告)日：2024-11-28

申请号：US18789349

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Shahaji B. More ,  Shih-Chieh Chang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.