公开(公告)号：US12237393B2

公开(公告)日：2025-02-25

申请号：US17853955

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US12237333B2

公开(公告)日：2025-02-25

申请号：US17222495

申请日：2021-04-05

Applicant: Tokyo Electron Limited

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A first transistor tier is formed over a substrate, positioned in a first tier of the semiconductor device and includes bottom transistors extending along a horizontal direction parallel to the substrate. A first segment of a first conductive plane is formed in the first tier and adjacent to a first side of the first transistor tier, spans a height of the first transistor tier, and is connected to the first transistor tier. A second transistor tier is formed over the first transistor tier, positioned in a second tier of the semiconductor device and includes top transistors extending along the horizontal direction. A second segment of the first conductive plane is formed in the second tier and adjacent to a first side of the second transistor tier, positioned over and connected to the first segment of the first conductive plane, and spans a height of the second transistor tier.

公开(公告)号：US20250062126A1

公开(公告)日：2025-02-20

申请号：US18818265

申请日：2024-08-28

Applicant: Tessera LLC

Inventor： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/28 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H10K71/20 ,  H10N70/00

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US12232329B2

公开(公告)日：2025-02-18

申请号：US18359248

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US20250056863A1

公开(公告)日：2025-02-13

申请号：US18932839

申请日：2024-10-31

Applicant: SK keyfoundry Inc.

Inventor： Min Kuck CHO ,  Jae Hoon KIM ,  Seung Hoon LEE

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/35

Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate

公开(公告)号：US20250056804A1

公开(公告)日：2025-02-13

申请号：US18931775

申请日：2024-10-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Xiaoxin Liu ,  Lei Xue ,  Zhiliang Xia

IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423

Abstract: A memory device includes a stack structure and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers in a first direction. The channel structure extends through the stack structure along the first direction. The channel structure includes a blocking layer, a storage layer, a tunneling layer, and a semiconductor channel stacked along a second direction intersecting the first direction. The dielectric layers extend through the blocking layer, the storage layer, and the tunneling layer along the second direction and are in contact with the semiconductor channel.

公开(公告)号：US20250054766A1

公开(公告)日：2025-02-13

申请号：US18772359

申请日：2024-07-15

Applicant: Infineon Technologies Austria AG

Inventor： Clemens Ostermaier ,  Nicholas Dellas

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778

Abstract: A method includes: providing a Group III nitride-based substrate having a first major surface and a doped Group III nitride region; forming a first passivation layer configured as a hydrogen diffusion barrier on the first major surface; forming a first opening in the first passivation layer and exposing at least a portion of the doped Group III nitride region from the first passivation layer; activating a first doped Group III nitride region whilst the first passivation layer is located on the first major surface and the doped Group III nitride region is at least partly exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the doped Group III nitride region; forming a second opening in the first and second passivation layers and exposing a portion of the doped Group III nitride region; and forming a contact in the second opening.

公开(公告)号：US12225725B2

公开(公告)日：2025-02-11

申请号：US17650700

申请日：2022-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： So Hyeon Lee

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H10B41/27 ,  H10B41/30 ,  H10B43/27 ,  H10B43/30 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs.

公开(公告)号：US12219763B2

公开(公告)日：2025-02-04

申请号：US17744092

申请日：2022-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisung Cheon ,  Byunggon Park ,  Joowon Park ,  Sangjun Hong ,  Jinsoo Lim

IPC: H10B43/27 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole.

公开(公告)号：US20250040240A1

公开(公告)日：2025-01-30

申请号：US18361255

申请日：2023-07-28

Applicant: International Business Machines Corporation

Inventor： Shay Reboh ,  Julien Frougier ,  Leon Sigal ,  Ruilong Xie

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.