公开(公告)号：US20240363724A1

公开(公告)日：2024-10-31

申请号：US18307025

申请日：2023-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ding-Kang Shih

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/66439 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

摘要： A method of manufacturing a semiconductor device includes: forming a stack of semiconductor layers and sacrificial layers alternately arranged over a substrate; patterning the stack to form a stacking structure on the substrate; disposing a sacrificial gate structure on the substrate, where the sacrificial gate structure covers a portion of the stacking structure; removing portions of the stacking structure not overlapped with the sacrificial gate structure; disposing source/drain regions at opposite sides of the sacrificial gate structure, where the semiconductor layers in the remained stacking structure connect between the source/drain regions; removing the sacrificial gate structure and rest of the sacrificial layers to form a cavity accessibly revealing the semiconductor layers; forming a semiconductor material to cover the semiconductor layers; performing a thermal process to transfer the semiconductor material into a Si-containing layer and a Ge-containing layer, where the Si-containing layer is disposed over the semiconductor layers, and the Ge-containing layer is interposed between the Si-containing layer and the semiconductor layers; and forming a gate structure in the cavity and over the remained stacking structure.

公开(公告)号：US20240363707A1

公开(公告)日：2024-10-31

申请号：US18769182

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

公开(公告)号：US20240363360A1

公开(公告)日：2024-10-31

申请号：US18769414

申请日：2024-07-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsing OU YANG

IPC分类号： H01L21/311 ,  H01L21/027

CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/31116

摘要： This disclosure provides methods of patterning a semiconductor structure. A first resist layer is patterned to form a first opening in the first resist layer. A second resist layer under the first resist layer is patterned to extend the first opening into the second resist layer, where a top surface of an oxide in the second resist layer is higher than a bottom surface of the first opening. The oxide and the second resist layer are simultaneously etched by a first etching process, where a first etching rate of the oxide is close to a second etching rate of the second resist layer. The oxide and a silicon-containing layer under the oxide are etched by a second etching process to form a second opening below the first opening, where a third etching rate of the oxide is higher than a fourth etching rate of the silicon-containing layer.

公开(公告)号：US12133376B2

公开(公告)日：2024-10-29

申请号：US17506833

申请日：2021-10-21

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Fan Rao ,  Seongjin Kong

IPC分类号： H10B12/00 ,  H01L21/308 ,  H01L21/311

CPC分类号： H10B12/485 ,  H01L21/3086 ,  H01L21/31111

摘要： A method for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes a plurality of active areas separated from each other, the active areas extend along a first direction, and each active area includes a bit line contact area and two electrical connection areas located on both sides of the bit line contact area; forming first mask layers, which are separated from each other, on the substrate; forming spacer layers on two opposite side walls of each first mask layer; forming second mask layers between adjacent first mask layers; removing the spacer layers between the first mask layers and the second mask layers; and etching the substrate by using the first mask layers and the second mask layers as masks to form a bit line contact hole.

公开(公告)号：US12131949B2

公开(公告)日：2024-10-29

申请号：US18362676

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Yu Chen ,  Chung-Liang Cheng

IPC分类号： H01L21/768 ,  H01L21/225 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L21/76879 ,  H01L21/2254 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76882 ,  H01L29/401 ,  H01L29/41791 ,  H01L21/31122 ,  H01L21/76831 ,  H01L29/456

摘要： A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US12131900B2

公开(公告)日：2024-10-29

申请号：US17873793

申请日：2022-07-26

申请人： Applied Materials, Inc.

发明人： Bhaskar Jyoti Bhuyan ,  Mark Saly ,  Lakmal C. Kalutarage ,  Thomas Joseph Knisley

IPC分类号： C23C16/00 ,  C23C16/02 ,  C23C16/30 ,  C23C16/455 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L21/0217 ,  C23C16/0245 ,  C23C16/308 ,  C23C16/45525 ,  H01L21/02118 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/31138

摘要： Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.

公开(公告)号：US12129418B2

公开(公告)日：2024-10-29

申请号：US17743080

申请日：2022-05-12

申请人： ENTEGRIS, INC.

发明人： Hsing-Chen Wu ,  Min-Chieh Yang ,  Ming-Chi Liao ,  Wen Hua Tai ,  Wei-Ling Lan

IPC分类号： C09K13/06 ,  C09K13/00 ,  C09K13/04 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213

CPC分类号： C09K13/06 ,  C09K13/00 ,  C09K13/04 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/311 ,  H01L21/31105 ,  H01L21/32134

摘要： The present invention relates to compositions and methods for selectively etching silicon nitride in the presence of silicon oxide, polysilicon and/or metal silicides at a high etch rate and with high selectivity. Additives are described that can be used at various dissolved silica loading windows to provide and maintain the high selective etch rate and selectivity.

公开(公告)号：US20240357821A1

公开(公告)日：2024-10-24

申请号：US18763037

申请日：2024-07-03

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YUAN-YUAN LIN

IPC分类号： H10B43/27 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H10B43/27 ,  H01L21/7682 ,  H01L23/5329 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/31127 ,  H01L23/5226

摘要： The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor pattern structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.

公开(公告)号：US20240355642A1

公开(公告)日：2024-10-24

申请号：US18304367

申请日：2023-04-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wei-Chuan FANG

IPC分类号： H01L21/56 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/56 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32133

摘要： The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure includes alternatively disposed first nitride portions and second nitride portions wrapping portions of an oxide layer, a dielectric layer disposed between one of the first nitride portions and one of the second nitride portions, a top nitride surrounded by the one of the first nitride portions or the one of the second nitride portions, a filling material, and a cap layer disposed on the filling material; forming a plurality of trenches to expose the portions of the oxide layer wrapped by the first nitride portions and the second nitride portions; forming air gaps by removing the portions of the oxide layer; and conformally forming an encapsulating layer on inner sidewalls of the trenches to encapsulate the air gaps.

公开(公告)号：US12125908B2

公开(公告)日：2024-10-22

申请号：US17751198

申请日：2022-05-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ling Chan ,  Meng-Yueh Liu ,  Wei-Ken Lin

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/7833 ,  H01L21/2254 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.