摘要:
A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.
摘要:
A semiconductor device includes a first bidirectional diode of a ring shape surrounding a central region and including a first connection section and a second connection section which is provided to the inner side of the ring shape from the first connection section, a semiconductor element in the central region including a first semiconductor element electrode, a second semiconductor element electrode, and a control electrode, the first semiconductor element electrode electrically connected to the first connection section and the second semiconductor element electrode electrically connected to the control electrode, a first resistor including a first resistor electrode and a second resistor electrode, the first resistor electrode electrically connected to the second connection section and the control electrode, a second bidirectional diode electrically connected to the second resistor electrode and to the second semiconductor element electrode, and a second resistor element electrically connected to the second resistor electrode.
摘要:
In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.
摘要:
In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n− type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm−3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.
摘要:
A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.
摘要:
During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.
摘要:
An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ccb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (
摘要:
A semiconductor device of this invention (an IGBT with a built-in diode) includes: an n−-type drift layer 1; a p-type channel region 2 that is arranged in contact with the surface side of this n−-type drift layer 1; a gate electrode 5 that is provided in a trench T provided so as to penetrate this p-type channel region 2 and reach to the n−-type drift layer 1 through a gate insulating film 3; an n-type source region 4 that is provided so as to contact the trench T on the surface side of the p-type channel region 2; a high-concentration n-type region 6 that is arranged in contact with the back side of the n−-type drift layer 1; and a high-concentration p-type region 7 that is arranged in contact with the back side of this high-concentration n-type region 6; in which a junction of the high-concentration n-type region 6 and the high-concentration p-type region 7 is a tunnel junction. According to this semiconductor device, it is possible to form the IGBT and the diode on a single chip. Moreover, it is possible to avoid problems of “snap back” and “current concentration.”
摘要:
A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.
摘要:
A method for manufacturing a semiconductor device is provided. The semiconductor device includes a cathode region of the diode, a first buffer region adjacent to the cathode region at a rear surface side of a semiconductor substrate, a collector region of the IGBT, and a second buffer region adjacent to the collector region at the rear surface side. The method includes forming the step portion on the front surface so that the thin portion and the thick portion are formed in the semiconductor substrate, and injecting n-type impurities to a range on the front surface extending across the thin and thick portions so that the first buffer region and the second buffer region are formed.