公开(公告)号：US11435636B2

公开(公告)日：2022-09-06

申请号：US16712007

申请日：2019-12-12

申请人： LG DISPLAY CO., LTD.

发明人： Kum Mi Oh ,  In Sang Jung ,  Sung Hoon Kim

IPC分类号： H01L21/338 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1362

摘要： Discussed is a method of manufacturing a LCD device, the method including: forming a gate in each of a plurality of pixel areas on a substrate; forming a gate insulator to cover the gate; forming a semiconductor layer on the gate insulator, and forming a photoresist (PR) on the semiconductor layer; doping high-concentration impurities at the semiconductor layer by using the photoresist (PR) as a mask to form an active layer, a source, and a drain; and doping low-concentration impurities at the semiconductor layer by using the photoresist (PR) as the mask to form a lightly doped drain (LDD) between the active layer and the source and between the active layer and the drain.

公开(公告)号：US10971612B2

公开(公告)日：2021-04-06

申请号：US16555036

申请日：2019-08-29

申请人： Cree, Inc.

发明人： Kyle Bothe ,  Evan Jones ,  Dan Namishia ,  Chris Hardiman ,  Fabian Radulescu ,  Terry Alcorn ,  Scott Sheppard ,  Bruce Schmukler

IPC分类号： H01L31/101 ,  H01L21/338 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/45 ,  H01L21/306 ,  H01L21/765 ,  H01L29/66 ,  H01L29/417 ,  H03F3/21 ,  H03F1/02 ,  H01L21/285

摘要： A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

公开(公告)号：US10854600B2

公开(公告)日：2020-12-01

申请号：US16577629

申请日：2019-09-20

申请人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

发明人： Justin Andrew Parke ,  Eric J. Stewart ,  Robert S. Howell ,  Howell George Henry ,  Bettina Nechay ,  Harlan Carl Cramer ,  Matthew Russell King ,  Shalini Gupta ,  Ronald G. Freitag ,  Karen Marie Renaldo

IPC分类号： H01L21/338 ,  H01L27/088 ,  H01L21/8252 ,  H01L21/308 ,  H01L29/66 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06

摘要： A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

公开(公告)号：US10797153B2

公开(公告)日：2020-10-06

申请号：US16025085

申请日：2018-07-02

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Abhishek Banerjee ,  Piet Vanmeerbeek ,  Peter Moens ,  Marnix Tack ,  Woochul Jeon ,  Ali Salih

IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

摘要： A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

公开(公告)号：US10522651B2

公开(公告)日：2019-12-31

申请号：US15823029

申请日：2017-11-27

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Zhuofan Chen ,  Haiyang Zhang

IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

摘要： The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.

公开(公告)号：US10128376B2

公开(公告)日：2018-11-13

申请号：US15613955

申请日：2017-06-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyungin Choi ,  Changhwa Kim ,  Taegon Kim ,  Hyunchul Song

IPC分类号： H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/78 ,  H01L29/06

摘要： Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate, a device isolation layer that defines an active region, an active fin vertically protruding from the active region of the substrate and extending in a horizontal direction, a gate structure traversing the active fin, and a source/drain contact on the active fin on a side of the gate structure. The gate structure may include a gate pattern and a capping pattern on the gate pattern, and the capping pattern may have impurities doped therein. The capping pattern may include a first part and a second part between the first part and the gate pattern. The first and second parts may have impurity concentrations different from each other.

公开(公告)号：US10128158B2

公开(公告)日：2018-11-13

申请号：US15821345

申请日：2017-11-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. Anderson ,  Alain Loiseau

IPC分类号： H01L21/00 ,  H01L21/338 ,  H01L21/336 ,  H01L27/148 ,  H01L29/80 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

摘要： An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

公开(公告)号：US10128157B2

公开(公告)日：2018-11-13

申请号：US15674002

申请日：2017-08-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. Anderson ,  Alain Loiseau

IPC分类号： H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

摘要： An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

公开(公告)号：US10020221B1

公开(公告)日：2018-07-10

申请号：US15787107

申请日：2017-10-18

申请人： International Business Machines Corporation

发明人： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Hao Tang

IPC分类号： H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L21/338 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/66

CPC分类号： H01L21/76224 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions includes a dielectric layer; and a doped region on the dielectric layer.

公开(公告)号：US10002803B2

公开(公告)日：2018-06-19

申请号：US15497608

申请日：2017-04-26

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC分类号： H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/66 ,  H01L21/84 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12 ,  H01L21/683

CPC分类号： H01L22/22 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823885 ,  H01L21/84 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2221/68359

摘要： Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.