公开(公告)号：US11972945B2

公开(公告)日：2024-04-30

申请号：US17743947

申请日：2022-05-13

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Kenichi Okazaki ,  Yukinori Shima

IPC分类号： H01L21/02 ,  G02F1/1368 ,  H01L21/321 ,  H01L21/426 ,  H01L21/441 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/385

CPC分类号： H01L21/02315 ,  G02F1/1368 ,  H01L21/02518 ,  H01L21/321 ,  H01L21/426 ,  H01L21/441 ,  H01L21/47635 ,  H01L21/823437 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  G02F1/13685 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/385

摘要： A semiconductor device having favorable electrical characteristics is provided. The semiconductor device is manufactured by a first step of forming a semiconductor layer containing a metal oxide, a second step of forming a first insulating layer, a third step of forming a first conductive film over the first insulating layer, a fourth step of etching part of the first conductive film to form a first conductive layer, thereby forming a first region over the semiconductor layer that overlaps with the first conductive layer and a second region over the semiconductor layer that does not overlap with the first conductive layer, and a fifth step of performing first treatment on the conductive layer. The first treatment is plasma treatment in an atmosphere including a mixed gas of a first gas containing an oxygen element but not containing a hydrogen element, and a second gas containing a hydrogen element but not containing an oxygen element.

公开(公告)号：US20220367691A1

公开(公告)日：2022-11-17

申请号：US17660729

申请日：2022-04-26

申请人： Japan Display Inc.

发明人： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/426 ,  H01L29/786

摘要： According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

公开(公告)号：US11329166B2

公开(公告)日：2022-05-10

申请号：US15774930

申请日：2016-11-09

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Yasuharu Hosaka ,  Yukinori Shima ,  Masataka Nakada ,  Masami Jintyou

IPC分类号： H01L29/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/04 ,  H01L51/50 ,  G02F1/1368 ,  H01L21/426 ,  H01L27/12 ,  H01L27/32

摘要： In a transistor that includes an oxide semiconductor, a change in electrical characteristics is suppressed and the reliability is improved.
A semiconductor device that includes a transistor is provided. The transistor includes a first conductive film that functions as a first gate electrode, a first gate insulating film, a first oxide semiconductor film that includes a channel region, a second gate insulating film, and a second oxide semiconductor film and a second conductive film that function as a second gate electrode. The second oxide semiconductor film includes a region higher in carrier density than the first oxide semiconductor film. The second conductive film includes a region in contact with the first conductive film.

公开(公告)号：US11309336B2

公开(公告)日：2022-04-19

申请号：US16922438

申请日：2020-07-07

申请人： Japan Display Inc.

发明人： Isao Suzumura

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/12 ,  G02F1/1368 ,  H01L27/32 ,  H01L29/40 ,  H01L29/423 ,  H01L21/426

摘要： The purpose of the present invention is to decrease the resistance of the drain and source in the TFT of the oxide semiconductor as well as to have stable Vd-Id characteristics of the TFT. The structure of the present invention is as follows: A display device having plural pixels including thin film transistors (TFT) having oxide semiconductor films comprising: a gate insulating film formed on the oxide semiconductor film, an aluminum oxide film formed on the gate insulating film, a gate electrode formed on the aluminum oxide film, a side spacer formed on both sides of the gate electrode, and an interlayer insulating film formed on the gate electrode, the side spacer, a drain and a source, wherein in a plan view, and in a direction from the drain to the source, a length of the gate electrode is shorter than a length of the aluminum oxide film.

公开(公告)号：US20220115542A1

公开(公告)日：2022-04-14

申请号：US17394204

申请日：2021-08-04

申请人： LG Display Co., Ltd.

发明人： JeongSuk YANG

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/426 ,  H01L29/66

摘要： A thin film transistor includes an active layer, a gate electrode spaced apart from and partially overlapped with the active layer, and a gate insulating film between the active layer and the gate electrode, wherein the active layer includes a channel portion overlapped with the gate electrode, a conductorization portion which is not overlapped with the gate electrode, and a gradient portion between the channel portion and the conductorization portion and not overlapped with the gate electrode, the conductorization portion and the gradient portion of the active layer are doped with a dopant, the gate insulating film covers an upper surface of the active layer facing the gate electrode during doping of the active layer, and in the gradient portion, a concentration of the dopant increases along a direction from the channel portion toward the conductorization portion. A display device may also include the thin film transistor.

公开(公告)号：US20210327722A1

公开(公告)日：2021-10-21

申请号：US17179533

申请日：2021-02-19

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Toshimasa HARA ,  Katsunori DANNO ,  Motohisa KADO ,  Hayate YAMANO

IPC分类号： H01L21/385 ,  H01L21/426 ,  H01L21/477

摘要： The present disclosure provides a method for producing a semiconductor element that can lower the potential risk of malfunction. The production method of the disclosure is a method for producing a semiconductor element which includes providing a semiconductor element precursor, the precursor having a metal electrode layer formed on the surface of a gallium oxide-based single crystal semiconductor layer and a dopant doped in at least part of an exposed portion on the surface of the gallium oxide-based single crystal semiconductor layer where the metal electrode layer is not layered, and annealing treatment of the semiconductor element precursor whereby the dopant is diffused to a portion of the gallium oxide-based single crystal semiconductor layer that are overlapping with the metal electrode layer in the layering direction, to form a Schottky junction between the gallium oxide-based single crystal semiconductor layer and the metal electrode layer.

公开(公告)号：US11152225B1

公开(公告)日：2021-10-19

申请号：US17179533

申请日：2021-02-19

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Toshimasa Hara ,  Katsunori Danno ,  Motohisa Kado ,  Hayate Yamano

IPC分类号： H01L21/00 ,  H01L21/385 ,  H01L21/477 ,  H01L21/426

摘要： The present disclosure provides a method for producing a semiconductor element that can lower the potential risk of malfunction. The production method of the disclosure is a method for producing a semiconductor element which includes providing a semiconductor element precursor, the precursor having a metal electrode layer formed on the surface of a gallium oxide-based single crystal semiconductor layer and a dopant doped in at least part of an exposed portion on the surface of the gallium oxide-based single crystal semiconductor layer where the metal electrode layer is not layered, and annealing treatment of the semiconductor element precursor whereby the dopant is diffused to a portion of the gallium oxide-based single crystal semiconductor layer that are overlapping with the metal electrode layer in the layering direction, to form a Schottky junction between the gallium oxide-based single crystal semiconductor layer and the metal electrode layer.

公开(公告)号：US20210043756A1

公开(公告)日：2021-02-11

申请号：US17079853

申请日：2020-10-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Yee-Chia Yeo

IPC分类号： H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L27/088 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L21/477 ,  H01L21/8234 ,  H01L21/8256 ,  H01L29/786 ,  H01L27/06 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/423 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24

摘要： Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US20200058505A1

公开(公告)日：2020-02-20

申请号：US16665139

申请日：2019-10-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L21/426 ,  H01L21/308 ,  H01L21/266 ,  H01L21/3215 ,  H01L21/311

摘要： Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

公开(公告)号：US20200006535A1

公开(公告)日：2020-01-02

申请号：US16570663

申请日：2019-09-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jean-Pierre Colinge ,  Carlos H. Diaz ,  Yee-Chia Yeo

IPC分类号： H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L27/088 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L21/477 ,  H01L21/8234 ,  H01L21/8256 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24

摘要： Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.