公开(公告)号：US20240363392A1

公开(公告)日：2024-10-31

申请号：US18765940

申请日：2024-07-08

Applicant: Applied Materials, Inc.

Inventor： Daihua Zhang ,  Yingdong Luo ,  Mingwei Zhu ,  Hou T. Ng ,  Sivapackia Ganapathiappan ,  Nag B. Patibandla

IPC: H01L21/70 ,  H01L21/02 ,  H01L21/027 ,  H01L25/075 ,  H01L27/15 ,  H01L33/00 ,  H01L33/44 ,  H01L33/50 ,  H01L33/58 ,  H01L33/62

CPC classification number: H01L21/70 ,  H01L21/02104 ,  H01L21/027 ,  H01L21/707 ,  H01L25/0753 ,  H01L27/153 ,  H01L33/00 ,  H01L33/0093 ,  H01L33/44 ,  H01L33/505 ,  H01L33/58 ,  H01L33/62 ,  H01L2933/0041 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a color conversion layer over each of a plurality of light emitting diodes, and a plurality of isolation walls separating adjacent micro-LEDs of the array.

公开(公告)号：US20240249052A1

公开(公告)日：2024-07-25

申请号：US18624471

申请日：2024-04-02

Applicant: Applied Materials, Inc.

Inventor： Debkalpo Das ,  Raman K. Nurani ,  Ramachandran Subramanian ,  Bibhavendra Singh ,  Bharath Sundar

IPC: G06F30/33 ,  G06F18/213 ,  G06F18/214 ,  H01L21/70

CPC classification number: G06F30/33 ,  G06F18/213 ,  G06F18/214 ,  H01L21/702

Abstract: A method includes obtaining sensor data associated with a deposition process performed in a process chamber to deposit film on a surface of a substrate. A plurality of physics-based outputs are generated using a transformation function and the sensor data. The transformation function is used to at least one of estimate site availability for growth at an equilibrium condition for the process chamber or estimate boundary layer thickness in an equilibrium condition for the process chamber. The physics-based outputs are mapped to a training set and a virtual model is trained based on the training set and the sensor data. The virtual model is trained to generate predictive metrology data associated with the film.

公开(公告)号：US12020978B2

公开(公告)日：2024-06-25

申请号：US17137500

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Sam Gnana Sabapathy

IPC: G01R31/317 ,  G01R31/3187 ,  G06F30/30 ,  H01L21/70

CPC classification number: H01L21/70 ,  G01R31/31716 ,  G06F30/30 ,  G01R31/3187

Abstract: A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

公开(公告)号：US20240203972A1

公开(公告)日：2024-06-20

申请号：US18589812

申请日：2024-02-28

Applicant: TDK Corporation

Inventor： Kazuhiro YOSHIKAWA ,  Takeshi OOHASHI ,  Koichi TSUNODA ,  Mitsuhiro TOMIKAWA

IPC: H01L27/01 ,  H01L21/70 ,  H01L23/00

CPC classification number: H01L27/01 ,  H01L21/702 ,  H01L24/05 ,  H01L24/03 ,  H01L2224/03462 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05582 ,  H01L2224/05638 ,  H01L2224/05655 ,  H01L2924/01014

Abstract: Disclosed herein is an electronic component that includes: a substrate; a capacitor on the substrate; a first insulating resin layer embedding therein the capacitor; an inductor provided on the first insulating resin layer and connected to the capacitor, the inductor including a conductor pattern; a second insulating resin layer embedding therein the inductor; a third insulating resin layer on the second insulating resin layer; a post conductor having a lower end and an upper end and penetrating the third insulating resin layer such that the lower end of the post conductor is connected to the inductor; and a terminal electrode on the third insulating resin layer and connected to the upper end of the post conductor. In a thickness direction of the substrate, the height of the post conductor is larger than a thickness of a conductor pattern constituting the inductor.

公开(公告)号：US11776947B2

公开(公告)日：2023-10-03

申请号：US17206656

申请日：2021-03-19

Applicant: TDK CORPORATION

Inventor： Yusuke Oba ,  Kenichi Yoshida ,  Takashi Ohtsuka ,  Yuichiro Okuyama ,  Tomoya Hanai ,  Yu Fukae

IPC: H01L25/18 ,  H01L27/01 ,  H01L21/70 ,  H01L21/78 ,  H01L49/02

CPC classification number: H01L25/18 ,  H01L21/707 ,  H01L21/78 ,  H01L27/016 ,  H01L28/10 ,  H01L28/40

Abstract: Disclosed herein is an electronic component that includes a substrate, a functional layer formed on the substrate and having a plurality of alternately stacked conductor layers and insulating layers, and a plurality of terminal electrodes provided on an uppermost one of the insulating layers. The uppermost one of the insulating layers has a substantially rectangular planar shape and has a protruding part protruding in a planar direction from at least one side in a plan view.

公开(公告)号：US20230253377A1

公开(公告)日：2023-08-10

申请号：US18304087

申请日：2023-04-20

Applicant: eLux Inc.

Inventor： Paul J Schuele ,  Kenji Sasaki ,  Kurt Ulmer ,  Jong-Jan Lee

IPC: H01L25/075 ,  H01L33/48 ,  H01L33/38 ,  H01L21/673 ,  H01L21/70

CPC classification number: H01L25/0753 ,  H01L33/486 ,  H01L33/38 ,  H01L21/67316 ,  H01L21/67343 ,  H01L21/70 ,  H01L2933/0033 ,  H01L2933/0066

Abstract: A microLED mass transfer stamping system includes a stamp substrate with an array of trap sites, each configured with a columnar-shaped recess to temporarily secure a keel extended from a bottom surface of a microLED. In the case of surface mount microLEDs, the keel is electrically nonconductive. In the case of vertical microLEDs, the keel is an electrically conductive second electrode. The stamping system also includes a fluidic assembly carrier substrate with an array of wells having a pitch separating adjacent wells that matches the pitch separating the stamp substrate trap sites. A display substrate includes an array of microLED pads with the same pitch as the trap sites. The stamp substrate top surface is pressed against the display substrate, with each trap site interfacing a corresponding microLED site, and the microLEDs are transferred. Fluidic assembly stamp substrates are also presented for use with microLEDs having keels or axial leads.

公开(公告)号：US11695005B2

公开(公告)日：2023-07-04

申请号：US17194765

申请日：2021-03-08

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1033 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the invention are directed to a semiconductor-based structure. A non-limiting example of the semiconductor-based structure includes a fin formed over a substrate. A tunnel is formed through the fin to define an upper fin region and a lower fin region. A gate structure is configured to wrap around a circumference of the upper fin region.

公开(公告)号：US20230125974A1

公开(公告)日：2023-04-27

申请号：US18087892

申请日：2022-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Julien EL SABAHY ,  Larry BUFFLE ,  Stéphane BOUVIER ,  Frédéric VOIRON

IPC: H01L27/01 ,  H01L21/70

Abstract: A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

公开(公告)号：US11626327B2

公开(公告)日：2023-04-11

申请号：US17097578

申请日：2020-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuo-Cheng Chiang ,  Chung-Wei Hsu ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/308 ,  H01L21/033 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.

公开(公告)号：US20230070790A1

公开(公告)日：2023-03-09

申请号：US17800166

申请日：2021-10-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiyuan WANG ,  Feng QU

IPC: H01L27/01 ,  H01L49/02 ,  H01L21/70

Abstract: The present disclosure provides a substrate integrated with a passive device and a method for manufacturing the same, and belongs to the technical field of communications. The substrate integrated with a passive device according to the present disclosure includes a dielectric layer provided with a first connection via; and the passive device at least including an inductor. The inductor includes a plurality of first sub-structures and a plurality of second sub-structures respectively disposed on two opposite sides of the dielectric layer, and two adjacent first sub-structures of the plurality of first sub-structures are short-circuited by a corresponding one of the plurality of second sub-structures through the first connection via penetrating through the dielectric layer, so as to form an induction coil of the inductor.