公开(公告)号：US20230135000A1

公开(公告)日：2023-05-04

申请号：US17962634

申请日：2022-10-10

申请人： STMicroelectronics Pte Ltd

发明人： Yean Ching YONG ,  Jianhua JIN ,  Weiyang YAP ,  Voon Cheng NGWAN

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L21/765

摘要： A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.

公开(公告)号：US11621346B2

公开(公告)日：2023-04-04

申请号：US16611888

申请日：2018-05-08

申请人： C2Amps AB

发明人： Lars-Erik Wernersson ,  Olli-Pekka Kilpi

IPC分类号： H01L29/775 ,  H01L21/02 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

摘要： A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).

公开(公告)号：US20230085365A1

公开(公告)日：2023-03-16

申请号：US18056962

申请日：2022-11-18

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Ming-Yeh CHUANG

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/765

摘要： An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.

公开(公告)号：US11600708B2

公开(公告)日：2023-03-07

申请号：US16869563

申请日：2020-05-07

申请人： INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.

发明人： Hang Liao

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205

摘要： The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate, a doped group III-V layer, a gate conductor, a field plate, a first passivation layer, and a second passivation layer. The doped group III-V layer is disposed on the substrate. The gate conductor is disposed on the doped group III-V layer. The field plate is disposed on the gate conductor. The first passivation layer is located between the field plate and the gate conductor. The second passivation layer is located between the field plate and the first passivation layer.

公开(公告)号：US20230045843A1

公开(公告)日：2023-02-16

申请号：US17749071

申请日：2022-05-19

申请人： Richtek Technology Corporation

发明人： Yu-Ting Yeh ,  Kuo-Hsuan Lo ,  Chien-Hao Huang ,  Chu-Feng Chen ,  Wu-Te Weng

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/765 ,  H01L29/66

摘要： A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

公开(公告)号：US11527625B1

公开(公告)日：2022-12-13

申请号：US16917946

申请日：2020-07-01

申请人： MARVELL ASIA PTE, LTD.

发明人： Runzi Chang

IPC分类号： H01L29/40 ,  H01L21/765 ,  H01L27/088

摘要： A semiconductor device includes a core gate and a pair of isolation gates. The core gate has a first stack of two or more layers, the first stack including at least (i) a first dielectric layer having a first thickness and (ii) a first electrode layer. The isolation gates are formed on first and second sides of the core gate. The isolation gates are configured to electrically isolate the core gate. At least one of the isolation gates has a second stack of two or more layers, the second stack including at least (i) a second dielectric layer having a second thickness greater than the first thickness and (ii) a second electrode layer.

公开(公告)号：US20220336594A1

公开(公告)日：2022-10-20

申请号：US17230365

申请日：2021-04-14

申请人： Infineon Technologies Austria AG

发明人： Robert Haase ,  Timothy Henson

IPC分类号： H01L29/40 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L21/765 ,  H01L29/66

摘要： A semiconductor device is described. The semiconductor device includes: a plurality of stripe-shaped gates formed in a semiconductor substrate; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting field plates in the needle-shaped field plate trenches. The contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates. In the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches. Methods of producing the semiconductor device are also described.

公开(公告)号：US20220310803A1

公开(公告)日：2022-09-29

申请号：US17653719

申请日：2022-03-07

申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

发明人： Tadashi WATANABE ,  Yukinori NOSE

IPC分类号： H01L29/40 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

摘要： A semiconductor device includes a substrate, a nitride semiconductor layer formed on the substrate, a source electrode and a drain electrode formed in the nitride semiconductor layer. The source electrode and drain electrode are arranged side by side in a first direction. A gate electrode is formed on the nitride semiconductor layer between the source electrode and the drain electrode. A first protective film is formed on the nitride semiconductor layer, and covers the first protective film covering the source electrode, the drain electrode, and the gate electrode. A source field plate is formed on the first protective film between the gate electrode and the drain electrode in a plan view. A dielectric-breakdown inhibition portion includes a part positioned between an end of the source field plate and an end of the drain electrode in a sectional view, and inhibits dielectric breakdown of the first protective film.

公开(公告)号：US20220293779A1

公开(公告)日：2022-09-15

申请号：US17200916

申请日：2021-03-15

申请人： Vanguard International Semiconductor Corporation

发明人： Yang Du ,  Shin-Chen Lin ,  Chia-Ching Huang

IPC分类号： H01L29/778 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

摘要： A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.

公开(公告)号：US20220262908A1

公开(公告)日：2022-08-18

申请号：US17735369

申请日：2022-05-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng Ho ,  Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong ,  Jyun-Guan Jhou

IPC分类号： H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/765 ,  H01L21/8238

摘要： Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.