公开(公告)号：US12131956B2

公开(公告)日：2024-10-29

申请号：US17453212

申请日：2021-11-02

申请人： Tokyo Electron Limited

发明人： H. Jim Fulford ,  Mark I. Gardner ,  Partha Mukhopadhyay

IPC分类号： H01L21/8238 ,  H01L21/822 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823885 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/7827

摘要： A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

公开(公告)号：US12131952B2

公开(公告)日：2024-10-29

申请号：US18116736

申请日：2023-03-02

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/00 ,  B23K26/36 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01L21/822 ,  H01L23/544 ,  H01L21/683

CPC分类号： H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/78 ,  H01L23/544 ,  H01L21/67092 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20240355816A1

公开(公告)日：2024-10-24

申请号：US18762138

申请日：2024-07-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL YANG MING CHIAO TUNG UNIVERSITY

发明人： Chenming HU ,  Po-Tsang HUANG

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/12

CPC分类号： H01L27/0688 ,  H01L21/02496 ,  H01L21/8221 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/1207

摘要： An IC structure includes a first transistor, an interconnect structure, a dielectric layer, a polysilicon fin, and a second transistor. The first transistor is over a substrate. The interconnect structure is over the first transistor. The dielectric layer is over the interconnect structure. The polysilicon fin includes a first portion laterally extending over the dielectric layer, and a second portion extending through the dielectric layer to a metal material within the interconnect structure. The second transistor is formed on the first portion of the polysilicon fin.

公开(公告)号：US20240347506A1

公开(公告)日：2024-10-17

申请号：US18754172

申请日：2024-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Hsiu Chen ,  Ebin Liao ,  Hong-Ye Shih ,  Wen-Chih Chiou ,  Jia-Ling Ko

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/822 ,  H01L23/31 ,  H01L23/544 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L21/56 ,  H01L21/565 ,  H01L21/8221 ,  H01L23/544 ,  H01L25/50 ,  H01L23/3121 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06582

摘要： The disclosure provides a method of forming a package structure, and the method includes the following steps. A plurality of semiconductor components is bonded to a substrate. A grinding process is performed to thin the plurality of semiconductor components. The plurality of semiconductor components have a first total thickness variation (TTV) after performing the grinding process. A dielectric layer is formed on the substrate. A first chemical mechanical polishing (CMP) is performed to remove a first portion of the dielectric layer on top surfaces of the plurality of semiconductor components; and performing a second CMP process to remove a second portion of the dielectric layer between the plurality of semiconductor components and a portion of the plurality of semiconductor components. After performing the second CMP process, the plurality of semiconductor components has a second TTV less than the first TTV.

公开(公告)号：US12119264B2

公开(公告)日：2024-10-15

申请号：US17809595

申请日：2022-06-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Shogo Mochizuki ,  Gen Tsutsui

IPC分类号： H01L21/822 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L21/8221 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66787

摘要： Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) stacked above a second FET in a non-step nanosheet structure, and a bottom contact electrically connected to a first bottom source/drain (S/D) of the second FET through a portion of a first top S/D of the first FET.

公开(公告)号：US20240339453A1

公开(公告)日：2024-10-10

申请号：US18544670

申请日：2023-12-19

申请人： Samsung Electronics Co., Ltd.

发明人： Hyojin Kim ,  Donghoon Hwang ,  Inchan Hwang

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： A three-dimensional (3D) semiconductor device includes a substrate including a first surface and a second surface that are opposite to each other, a lower active region on the first surface of the substrate, the lower active region including a lower channel pattern and a lower source/drain pattern that are electrically connected to each other, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source/drain pattern that are electrically connected to each other, a dam pattern that vertically extends from the lower source/drain pattern to the upper source/drain pattern, a lower active contact electrically connected to the lower source/drain pattern, an upper active contact electrically connected to the upper source/drain pattern, and a vertical via that vertically extends along the dam pattern to electrically connect the lower active contact to the upper active contact.

公开(公告)号：US12113063B2

公开(公告)日：2024-10-08

申请号：US18103210

申请日：2023-01-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Chih Wen ,  Han-Ting Tsai ,  Chung-Te Lin

IPC分类号： H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N70/00 ,  H10N70/20 ,  H01L21/8234 ,  H10K59/00

CPC分类号： H01L27/0688 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/525 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N70/011 ,  H10N70/20 ,  H10N70/231 ,  H01L21/823475 ,  H10K59/00

摘要： A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

公开(公告)号：US20240332083A1

公开(公告)日：2024-10-03

申请号：US18738981

申请日：2024-06-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jerry Chang-Jui KAO ,  Hui-Zhong ZHUANG ,  Li-Chung HSU ,  Sung-Yen YEH ,  Yung-Chen CHIEN ,  Jung-Chan YANG ,  Tzu-Ying LIN

IPC分类号： H01L21/822 ,  H01L21/48 ,  H01L23/50 ,  H01L23/535

CPC分类号： H01L21/8221 ,  H01L21/4828 ,  H01L23/50 ,  H01L23/535

摘要： A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

公开(公告)号：US20240332082A1

公开(公告)日：2024-10-03

申请号：US18191895

申请日：2023-03-29

申请人： International Business Machines Corporation

发明人： Min Gyu Sung ,  Ruilong Xie ,  Julien Frougier ,  Chanro Park ,  Juntao Li

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/146 ,  H01L29/68

CPC分类号： H01L21/8221 ,  H01L21/823481 ,  H01L27/0225 ,  H01L27/14612 ,  H01L29/685

摘要： Embodiments of the invention are directed to an integrated circuit (IC) that includes a stacked device configuration having a top electronic device positioned over a bottom electronic device, along with an isolation region operable to electrically isolate at least a gate region of the top electronic device from a gate region of the bottom electronic device. The gate region of the top electronic device includes a first conductive material, and the gate region of the bottom electronic device includes a second conductive material that is different from the first conductive material.

公开(公告)号：US20240324251A1

公开(公告)日：2024-09-26

申请号：US18735002

申请日：2024-06-05

申请人： Kioxia Corporation

发明人： Sota MATSUMOTO ,  Takahito NISHIMURA

IPC分类号： H10B99/00 ,  H01L21/308 ,  H01L21/822 ,  H01L27/06 ,  H10B41/20 ,  H10B41/35 ,  H10B41/40

CPC分类号： H10B99/00 ,  H01L21/308 ,  H01L21/8221 ,  H01L27/0688 ,  H10B41/20 ,  H10B41/35 ,  H10B41/40

摘要： A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.