公开(公告)号：US06833312B2

公开(公告)日：2004-12-21

申请号：US10152830

申请日：2002-05-23

申请人： Kazutaka Yanagita ,  Mitsuharu Kohda ,  Kiyofumi Sakaguchi ,  Akira Fujimoto

发明人： Kazutaka Yanagita ,  Mitsuharu Kohda ,  Kiyofumi Sakaguchi ,  Akira Fujimoto

IPC分类号： H01L2130

CPC分类号： H01L21/67092 ,  Y10T156/1374 ,  Y10T156/19 ,  Y10T156/1906

摘要： This invention is to support a plate member such as a bonded substrate stack in a horizontal state without coming into contact with one surface of the member and also to efficiently progress separation. Separation is executed while arranging a bonded substrate stack (50) generated by bonding a seed substrate (10) to a handle substrate (20) such that the seed substrate (10) remains on the lower side. At the first stage, the peripheral portion is separated while causing a first substrate support section (101) to chuck and support the central portion of the lower surface of the bonded substrate stack (50). Then, at the second stage, the central portion is separated while causing a second substrate support section (102) to support the lower peripheral portion and side of the bonded substrate stack (50).

摘要翻译： 本发明是在水平状态下支撑诸如键合衬底叠层的板构件，而不与构件的一个表面接触并且还有效地进行分离。 在将通过将种子基板（10）接合到手柄基板（20）而产生的键合衬底叠层（50）使得种子基板（10）保持在下侧的同时进行分离。 在第一阶段，周边部分被分离，同时使第一基板支撑部分（101）夹持并支撑键合衬底叠层（50）的下表面的中心部分。 然后，在第二阶段，分离中心部分，同时使第二基板支撑部分（102）支撑键合衬底叠片（50）的下周边部分和侧面。

公开(公告)号：US06809007B2

公开(公告)日：2004-10-26

申请号：US10637978

申请日：2003-08-08

申请人： Paolo Valenti

发明人： Paolo Valenti

IPC分类号： H01L2130

CPC分类号： H01S5/028 ,  H01S5/4025

摘要： A carrier for treating photonic devices such as laser bars is provided with a recessed formation with a web surface for supporting the photonic device in contact therewith as well as at least one side surface forming an abutment surface for engaging a respective end facet of the photonic device. The photonic device is arranged in the recessed formation so that the lower surface of the photonic device is masked with respect to the treatment source, while at least one end facet of the photonic device engages at least one side surface by leaving exposed a surface to be treated. A protection member is placed in contact with the upper surface of the photonic device and the carrier with the photonic device arranged therein is exposed to the treatment source. The treatment is thus effective substantially exclusively on the surfaces of the end facets to be treated.

摘要翻译： 用于处理光子器件（例如激光棒）的载体设置有凹陷的形成物，其具有用于支撑与其接触的光子器件的腹板表面，以及形成用于接合光子器件的相应端面的邻接表面的至少一个侧表面 。 光子器件布置在凹陷结构中，使得光子器件的下表面相对于处理源被掩蔽，而光子器件的至少一个端面通过将暴露的表面留下来而与至少一个侧表面接合 治疗。 保护构件与光子器件的上表面接触并且布置有光子器件的载体暴露于处理源。 因此，处理基本上仅在待处理的端面的表面上有效。

公开(公告)号：US06790747B2

公开(公告)日：2004-09-14

申请号：US10268918

申请日：2002-10-09

申请人： Francois J. Henley ,  Nathan W. Cheung

发明人： Francois J. Henley ,  Nathan W. Cheung

IPC分类号： H01L2130

CPC分类号： H01L21/26506 ,  B81C1/0038 ,  B81C2201/0191 ,  B81C2201/0192 ,  H01L21/2658 ,  H01L21/76254

摘要： A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

摘要翻译： 一种用于从供体衬底（10）形成材料（12）的膜的技术。 该技术具有以选定的方式在表面下方的选定深度（20）处形成受应力区域的步骤。 诸如加压流体的能量源被引导到供体基底的选定区域，以在所选择的深度（20）处引发基底（10）的受控切割作用，因此所述切割动作提供扩张切割前缘以释放供体 来自供体衬底的剩余部分的材料。

公开(公告)号：US06753239B1

公开(公告)日：2004-06-22

申请号：US10407746

申请日：2003-04-04

申请人： Robert O. Conn

发明人： Robert O. Conn

IPC分类号： H01L2130

CPC分类号： H01L27/1203 ,  H01L21/76256 ,  H01L21/84 ,  Y10S438/928

摘要： A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.

摘要翻译： 将支撑结构晶片结合到部分或完全处理的器件晶片的上表面侧。 器件晶片包括具有延伸到器件晶片的衬底材料中的阱区的晶体管。 晶体管的源区和漏极区延伸到阱区。 在安装支撑结构之后，装置晶片从后侧变薄直到达到井区的底部。 为了减少源极和漏极结电容，可以继续蚀​​刻直到达到源极和漏极区域。 在一个实施例中，在随后的蚀刻步骤中除去所有的阱到衬底结，从而减少或消除所得晶体管的阱到衬底结电容。 阱电极和晶体管沟道之间的电阻降低，因为阱触点直接设置在晶体管的栅极正下方的器件晶片的背面。

公开(公告)号：US06746937B2

公开(公告)日：2004-06-08

申请号：US10443023

申请日：2003-05-22

申请人： Kevin L. Beaman

发明人： Kevin L. Beaman

IPC分类号： H01L2130

CPC分类号： H01L27/1203 ,  H01L29/78687

摘要： A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

摘要翻译： 公开了一种部分耗尽的具有最小电荷积聚和抑制浮体效应的绝缘体上硅绝缘体（SOI）衬底，以及其制造的简单方法。 在SOI衬底的两个相邻的外延硅层之间生长薄的Si / Ge外延层，并且作为硅外延生长的一部分。 薄的Si / Ge外延层在薄的Si / Ge外延层和相邻的外延硅层之间的界面处引入失配位错，这消除了衬底内不希望的电荷。

公开(公告)号：US06740567B2

公开(公告)日：2004-05-25

申请号：US09885784

申请日：2001-06-20

申请人： Mong-Song Liang ,  Syun-Ming Jang

发明人： Mong-Song Liang ,  Syun-Ming Jang

IPC分类号： H01L2130

CPC分类号： H01L21/768 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

摘要： Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the method there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication. Finally, there is then laminated the partially fabricated semiconductor integrated circuit microelectronic fabrication with the second substrate to mate the partially fabricated semiconductor integrated circuit microelectronic fabrication with the dielectric isolated metallization pattern to thus form a laminated completely fabricated semiconductor integrated circuit microelectronic fabrication. The method provides for enhanced efficiency when fabricating semiconductor integrated circuit microelectronic fabrications.

摘要翻译： 在制造半导体集成电路微电子制造的方法中，首先提供第一半导体衬底。 然后在第一半导体衬底上形成至少一个微电子器件，以从第一半导体衬底形成部分制造的半导体集成电路微电子制造。 在该方法中，还提供了第二衬底。 在第二衬底上还以反向顺序形成旨在与部分制造的半导体集成电路微电子制造配合的电介质隔离金属化图案。 最后，然后将部分制造的半导体集成电路微电子制造与第二衬底层压，以将部分制造的半导体集成电路微电子制造与介电隔离金属化图案配合，从而形成层叠的完全制造的半导体集成电路微电子制造。 该方法在制造半导体集成电路微电子制造时提供了增强的效率。

公开(公告)号：US06689669B2

公开(公告)日：2004-02-10

申请号：US10008313

申请日：2001-11-03

申请人： Anthony D. Kurtz ,  Alexander A. Ned

发明人： Anthony D. Kurtz ,  Alexander A. Ned

IPC分类号： H01L2130

CPC分类号： G01K7/226 ,  G01K7/003 ,  Y10S438/931 ,  Y10S438/977

摘要： Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.

摘要翻译： 可用于高温感测应用的半导体器件包括碳化硅衬底，二氧化硅层和晶体掺杂碳化硅的外层。 该器件是3C-SiC / SiO2 / SiC结构。 该结构可用于制造诸如压阻传感器，少数载流子装置等的高温装置。 晶体掺杂碳化硅与衬底介电隔离。 器件由包括将图案晶片结合到衬底晶片，选择性氧化和去除未掺杂硅的工艺形成，以及将掺杂硅转化为结晶碳化硅。 可以根据特定应用的所需性质来选择掺杂水平和碳化硅的晶体结构。

公开(公告)号：US06656818B1

公开(公告)日：2003-12-02

申请号：US09831374

申请日：2001-05-16

申请人： Jun Kishimoto

发明人： Jun Kishimoto

IPC分类号： H01L2130

CPC分类号： H01L21/02013 ,  B24B7/228

摘要： Provided is a manufacturing process for a semiconductor wafer according to which semiconductor wafers each with higher flatness can be manufactured with good efficiency from a wafer work having passed through a surface grinding step by enabling restriction of reduction in flatness in the vicinity of the center and in the outer peripheral edge portion of a surface ground wafer at the lowest level possible, and correction of the reduction in flatness of both portions with ease to planarize in a planarization or polishing step. When a semiconductor wafer fixed on a chuck table is surface ground using a cup shaped grinding wheel, the semiconductor wafer is ground toward the center thereof such that the grinding wheel cuts into the semiconductor wafer at the outer peripheral edge thereof and moves away from the semiconductor wafer at the central portion thereof and the ground semiconductor wafer is planarized according to a PACE method.

摘要翻译： 本发明提供一种半导体晶片的制造方法，通过能够限制中心附近的平坦度的降低，能够以通过表面研磨工序的晶片工作的效率高效率地制造具有较高的平坦度的半导体晶片， 表面接地晶片的外周缘部分可能处于最低水平，并且在平坦化或抛光步骤中易于平坦化地校正两部分的平坦度。 当使用杯形砂轮将固定在卡盘台上的半导体晶片进行表面磨削时，将半导体晶片朝向其中心研磨，使得砂轮在其外周边缘处切入半导体晶片并远离半导体 其中心部分的晶片和接地半导体晶片根据PACE方法平坦化。

公开(公告)号：US06653207B2

公开(公告)日：2003-11-25

申请号：US10093603

申请日：2002-03-11

申请人： Kazuyuki Ohya ,  Kazuhiro Otsu ,  Takeshi Nobukuni

发明人： Kazuyuki Ohya ,  Kazuhiro Otsu ,  Takeshi Nobukuni

IPC分类号： H01L2130

CPC分类号： H01L21/2007 ,  Y10S438/977

摘要： A process for the production of an electric part, comprising performing a circuit-parts-forming step including the introduction of impurities on one surface (surface A) of a semiconductor substrate, then bonding the surface A to a holding substrate, performing a back surface treatment step essentially including a polishing of an exposed surface (surface B) of the semiconductor substrate to a thickness of 100 &mgr;m or less to obtain an electric-part-formed thinned substrate and separating the thinned substrate from the holding substrate, wherein a resin composition containing a swelling inorganic compound (WC) is used for an adhesion layer and in the separating step the thinned substrate is separated from the holding substrate after decreasing the adhesive strength of the thinned substrate and the holding substrate by swelling the swelling inorganic compound (WC).

摘要翻译： 一种用于生产电气部件的方法，包括执行电路部分形成步骤，包括在半导体衬底的一个表面（表面A）上引入杂质，然后将表面A接合到保持衬底，执行背面 处理步骤基本上包括将半导体衬底的暴露表面（表面B）抛光至100μm以下的厚度，以获得电部件形成的薄化衬底，并将薄的衬底与保持衬底分离，其中树脂组合物 使用溶胀性无机化合物（WC）作为粘合层，在分离工序中，通过使溶胀性无机化合物（WC）膨胀，降低了薄板基板和保持基板的粘合强度后，将薄板基板与保持基板分离， 。

公开(公告)号：US06645836B2

公开(公告)日：2003-11-11

申请号：US09979305

申请日：2001-11-21

申请人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

发明人： Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Tohru Saitoh ,  Minoru Kubo

IPC分类号： H01L2130

CPC分类号： H01L29/1608 ,  C30B29/06 ,  C30B29/52 ,  C30B33/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02667 ,  H01L29/1054 ,  H01L29/165

摘要： A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and Sic microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.

摘要翻译： 对其上沉积有SiGeC晶体层8的Si衬底1进行退火，以在Si衬底1上形成退火的SiGeC晶体层10.退火的SiGeC晶体层包括晶格释放且几乎不具有位错的SiGeC晶体层7 ，以及分散在基体SiGeC晶体层7中的Sic微晶6.然后在退火的SiGeC晶体层10上沉积Si晶体层，形成几乎不具有位错的应变Si晶体层4。