公开(公告)号：US20240355900A1

公开(公告)日：2024-10-24

申请号：US18302010

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Man-Nung Su

IPC分类号： H01L29/66 ,  H01L23/00 ,  H01L23/12 ,  H01L29/775

CPC分类号： H01L29/66439 ,  H01L23/12 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/66742 ,  H01L29/775 ,  H01L24/94 ,  H01L29/0673 ,  H01L29/42392 ,  H01L2224/29138 ,  H01L2224/29186 ,  H01L2224/8301 ,  H01L2224/83193 ,  H01L2224/83896 ,  H01L2224/94 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

摘要： A semiconductor device and a forming method thereof are provided. The semiconductor device includes a device layer including a front side and a back side opposite to each other, a bonding layer disposed on the back side of the device layer, and a carrier substrate underlying the bonding layer. The device layer includes source/drain (S/D) structures, semiconductor channel layers connecting the S/D structures, and a gate structure disposed between the S/D structures and around each of the semiconductor channel layers, where the back side is planar and includes the S/D structures and the gate structure.

公开(公告)号：US12119338B2

公开(公告)日：2024-10-15

申请号：US18447655

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC分类号： H01L21/44 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

摘要： Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US12080675B2

公开(公告)日：2024-09-03

申请号：US17430691

申请日：2020-02-10

申请人： ROHM CO., LTD.

发明人： Kazunori Fuji

IPC分类号： H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L24/40 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/37 ,  H01L24/84 ,  H01L2224/32225 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/84893

摘要： Semiconductor device A1 of the disclosure includes: semiconductor element 11 having element obverse surface 11a and element reverse surface 11b spaced apart from each other in z direction (first direction) with first region 111 formed on the element obverse surface 11a; metal plate 31 (electrode member) disposed on the element obverse surface 11a and electrically connected to the first region 111; electrically conductive substrate 22A (first conductive member) disposed to face the element reverse surface 11b and bonded to the semiconductor element 11; electrically conductive substrate 22B (second conductive member) spaced apart from the conductive substrate 22A (first conductive member); and lead member 5 (connecting member) electrically connecting the metal plate 31 (electrode member) and the conductive substrate 22B (second conductive member). The lead member 5 (connecting member) is bonded to the metal plate 31 (electrode member) by laser welding. The semiconductor device of this configuration provides improved reliability.

公开(公告)号：US12062635B2

公开(公告)日：2024-08-13

申请号：US17451693

申请日：2021-10-21

申请人： Micron Technology, Inc.

发明人： Po Chih Yang ,  Yu Jen Chen ,  Po Chen Kuo ,  Shih Wei Liang

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L24/41 ,  H01L21/563 ,  H01L21/76871 ,  H01L23/3157 ,  H01L24/09 ,  H01L24/35 ,  H01L25/0657

摘要： Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Conductors may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The conductors may be in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device and between the conductors and the second semiconductor device. An encapsulant distinct from the dielectric material may cover the conductors, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

公开(公告)号：US11984373B2

公开(公告)日：2024-05-14

申请号：US17522327

申请日：2021-11-09

申请人： STMicroelectronics (Grenoble 2) SAS

发明人： Jerome Lopez

IPC分类号： H01L23/31 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52 ,  H01S5/02218 ,  H01S5/068

CPC分类号： H01L23/3114 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

摘要： An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

公开(公告)号：US11955409B2

公开(公告)日：2024-04-09

申请号：US17148257

申请日：2021-01-13

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Joan Rey Villarba Buot ,  Hong Bok We

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/12 ,  H01L23/66

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/12 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6638

摘要： A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

公开(公告)号：US11901317B2

公开(公告)日：2024-02-13

申请号：US17265273

申请日：2020-12-17

申请人： FUJIKURA LTD.

发明人： Kohei Matsumaru

IPC分类号： H01L23/66 ,  H01L23/12 ,  H01P3/08

CPC分类号： H01L23/66 ,  H01L23/12 ,  H01P3/082 ,  H01L2223/6677 ,  H01L2223/6683

摘要： The present invention reduces an electromagnetic coupling that can occur between a first signal line provided on a first substrate and a second signal line provided on a main surface of a second substrate on the first substrate side. A wireless module (10) includes an RFIC (28), a baseband IC (16), a first substrate (11) on which first signal lines (121 through 126) for transmitting a baseband signal are provided, and a second substrate (21) provided with second signal lines (2201 through 2232) for transmitting an RF signal on a main surface (211). The first substrate (11) is provided with a pseudo conductor wall (post wall 13) for shielding the first signal lines (121 through 126) and the second signal lines (2201 through 2232).

公开(公告)号：US11871524B2

公开(公告)日：2024-01-09

申请号：US16328646

申请日：2017-08-21

申请人： FUJIKURA LTD.

发明人： Masahiro Okamoto

IPC分类号： H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H05K3/00 ,  H05K3/10 ,  H05K1/00 ,  H01L23/12 ,  H05K1/02 ,  H01L23/498

CPC分类号： H05K3/46 ,  H01L23/12 ,  H05K1/00 ,  H05K1/03 ,  H05K1/112 ,  H05K1/183 ,  H05K3/0008 ,  H05K3/103 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/0251

摘要： A component-incorporated substrate of multi-layer structure includes: a plurality of printed wiring base members that are batch-laminated via an adhesive layer, with the plurality of printed wiring base members including a resin base member that includes a wiring pattern on at least one surface thereof and a via connected to the wiring pattern; an opening disposed in at least one printed wiring base member that is sandwiched on both sides by other printed wiring base members of the plurality of printed wiring base members; and an electronic component disposed in the opening. At least part of the wiring pattern of the printed wiring base member where the opening is formed is disposed in a frame shape surrounding the opening, in a periphery of the opening.

公开(公告)号：US20230402361A1

公开(公告)日：2023-12-14

申请号：US17840322

申请日：2022-06-14

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Shenghua Huang ,  Binbin Zheng ,  Shaopeng Dong ,  Songtao Lu ,  Rui Guo ,  Yangming Liu ,  Bo Yang ,  Ning Ye

IPC分类号： H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  G06K19/077 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L23/12 ,  H01L23/3107 ,  H01L25/0657 ,  G06K19/07732 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2924/3512 ,  H01L2924/1511 ,  H01L2224/48135

摘要： A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions on the substrate where mechanical stresses develop in the device during singulation, such as at curves and/or discontinuous points around the outline of the substrate, to add strength to the substrate.

公开(公告)号：US11831300B2

公开(公告)日：2023-11-28

申请号：US16815097

申请日：2020-03-11

申请人： Murata Manufacturing Co., Ltd.

发明人： Koichiro Kawasaki ,  Taku Kikuchi

IPC分类号： H03H9/64 ,  H03H9/02 ,  H03H9/25 ,  H03H9/10 ,  H01L23/12

CPC分类号： H03H9/64 ,  H01L23/12 ,  H03H9/02834 ,  H03H9/02944 ,  H03H9/02992 ,  H03H9/1092 ,  H03H9/25 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/16235

摘要： An elastic wave filter apparatus includes at least one excitation electrode, a first electrode land, and second electrode lands provided on a first main surface of a device substrate including a piezoelectric layer. A signal terminal and metal members are provided on a second main surface of the device substrate. The first electrode land and the signal terminal are connected to a signal potential, and the second electrode lands and the metal members are connected to a ground potential. A first connection electrode connects the first electrode land and the signal terminal, and a second connection electrode connects at least one of the second electrode lands and at least one of the metal members. The at least one metal member connected to the second connection electrode overlaps at least a portion of the at least one excitation electrode across the device substrate.