公开(公告)号：US12237300B2

公开(公告)日：2025-02-25

申请号：US17113341

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Tyler Leuten ,  Yi Xu ,  Eleanor Patricia Paras Rabadam

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/52 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Integrated circuit assemblies may contain various mold, fill, and/or underfill materials. As these integrated circuit assemblies become ever smaller, it becomes challenging to prevent voids from forming within these materials, which may affect the reliability of the integrated circuit assemblies. Since integrated circuit assemblies are generally formed by electrically attaching integrated circuit dice on electronic substrates, the present description proposes injecting the mold, fill, and/or underfill materials through openings formed in the electronic substrate to fill voids that may form and/or to prevent the formation of the voids altogether.

公开(公告)号：US20250040028A1

公开(公告)日：2025-01-30

申请号：US18696838

申请日：2023-05-16

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Patrick LENHARDT

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  H01L23/367 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/02 ,  H01Q1/52 ,  H01Q9/04 ,  H04B1/00 ,  H04B1/40 ,  H05K1/03 ,  H05K3/46

Abstract: There is described a radio frequency module, comprising: i) a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; and ii) a RF front-end functionality that is integrated in the stack. Further, an RF arrangement, a manufacture method and a use are described.

公开(公告)号：US20250038086A1

公开(公告)日：2025-01-30

申请号：US18696613

申请日：2023-09-26

Applicant: Hygon Information Technology Co., Ltd.

Inventor： Shuan Du ,  Xinchun Liu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure, a chip, an electronic apparatus, a manufacturing method for a package structure and a chip packaging method are provided. The package structure includes a first package substrate and at least one second package substrate, wherein the first package substrate includes a first interconnection layer, the first interconnection layer includes a first metal routing layer and a first dielectric layer which are alternately stacked, and the first interconnection layer is provided with at least one cavity; the second package substrate is arranged in the cavity and includes a second interconnection layer, wherein the second interconnection layer includes a second metal routing layer and a second dielectric layer which are alternately stacked, and the second dielectric layer includes an organic material; wherein a layout density of metal routings in the second metal routing layer is greater than a layout density of metal routings in the first metal routing layer.

公开(公告)号：US12211781B2

公开(公告)日：2025-01-28

申请号：US18383531

申请日：2023-10-25

Applicant: LG INNOTEK CO., LTD.

Inventor： Se Woong Na ,  Se Ho Myeong

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H05K1/18 ,  H05K3/46 ,  H05K1/11 ,  H05K3/00

Abstract: A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and exposed through the cavity; wherein the second insulating layer includes a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, and wherein a thickness of the first portion is smaller than a thickness of the second portion.

公开(公告)号：US12205857B2

公开(公告)日：2025-01-21

申请号：US17401971

申请日：2021-08-13

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kimmo Kaija

IPC: H05K3/40 ,  H01L23/043 ,  H01L23/13 ,  H01L23/498 ,  H05K3/30

Abstract: This disclosure describes an electronic component comprising a package with a top side and a bottom side and at least one electronic chip housed within an enclosure inside the package. The package comprises a package base on its top side and a metallic cap on its bottom side. At least one electronic chip is separated from the metallic cap by a gap and the metallic cap is attached to the package base to form an enclosure.

公开(公告)号：US20240429194A1

公开(公告)日：2024-12-26

申请号：US18610338

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO, ltd.

Inventor： EUNSU LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/433 ,  H01L25/065

Abstract: A semiconductor package includes a first package substrate, a dam structure on a top surface of the first package substrate and extending and surrounding a region of the first package substrate, a semiconductor chip on the top surface of the first package substrate, a plurality of posts on the top surface of the first package substrate and surrounding the semiconductor chip, and an underfill layer between the semiconductor chip and the first package substrate and surrounding a lower portion of each of the posts, wherein the posts are in the region of the top surface of the first package substrate surrounded by the dam structure.

公开(公告)号：US20240387197A1

公开(公告)日：2024-11-21

申请号：US18786580

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun-Ting Chen ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih ,  Ting-Yu Yeh ,  Chen-Hsuan Tsai

IPC: H01L21/56 ,  H01L21/304 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

公开(公告)号：US20240371711A1

公开(公告)日：2024-11-07

申请号：US18144164

申请日：2023-05-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Ting CHEN ,  Hung-Yi LIN ,  Cheng-Yuan KUNG

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/66 ,  H03H9/52 ,  H03H9/64

Abstract: A package structure is provided. The package structure includes an amplifier and a filter structure. The amplifier has an active surface. The filter structure is disposed over the amplifier, and communicates with the amplifier through a first signal path substantially vertical to the active surface of the amplifier.

公开(公告)号：US20240363515A1

公开(公告)日：2024-10-31

申请号：US18646799

申请日：2024-04-26

Applicant: STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.

Inventor： Jeonghan Kim ,  Soo Won Lee ,  Jian Xu ,  Hyoungill Min ,  Ruifeng Jiang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L23/13 ,  H01L25/16

Abstract: A semiconductor package structure and a forming method therefor are disclosed. The package structure includes: an encapsulant including a first and a second surfaces that are opposite and peripheral side surfaces, wherein the first surface is provided with protruding connection terminals, and junction between the first surface and the peripheral side surfaces are provided with four top corners; a substrate including a flip-chip area, wherein the flip-chip area is provided with four corner areas corresponding to four top corners of the encapsulant; trenches positioned in the substrate in the corner areas or around the corner areas or in the four corner areas and around the four corner areas at the same time; a high-modulus first underfill layer filling four trenches and spaces between the four trenches and the first surface of the encapsulant; and a low-modulus second underfill layer filling a remaining space between the encapsulant and the substrate.

公开(公告)号：US20240355723A1

公开(公告)日：2024-10-24

申请号：US18398090

申请日：2023-12-27

Applicant: JMJ Korea Co., Ltd.

Inventor： Yun Hwa CHOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/14 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48175 ,  H01L2224/73265 ,  H01L2924/181

Abstract: The present invention provides a semiconductor package including a lead frame pad 110 including at least one first substrate 111 and at least one second substrate 112 structurally bonded to one surface of the first substrate 111, at least one semiconductor chip 120 bonded onto the second substrate 112 by using a conductive adhesive, a lead frame lead 130 including at least one first terminal 131 structurally or electrically connected to the lead frame pad 110 and at least one second terminal 132 spaced apart from the lead frame pad 110 by a regular distance, an electrical connection member 140 electrically connecting the semiconductor chip 120 with the second terminal 132, and a housing 150 partially or entirely covering the semiconductor chip 120 and the lead frame pad 110. Here, the lead frame lead 130 is exposed and extended to the outside of the housing 150 and the thickness of the second substrate 112 is less than the thickness of the first substrate 111. Accordingly, the semiconductor chip 120 may be easily installed and excellent electrical conductivity may be realized.