公开(公告)号：US20240363506A1

公开(公告)日：2024-10-31

申请号：US18594792

申请日：2024-03-04

申请人： Amkor Technology Singapore Holding Pte Ltd.

发明人： Won Bae Bang ,  Kwang Seok Oh

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31

CPC分类号： H01L23/49805 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2924/15311

摘要： A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

公开(公告)号：US20240363458A1

公开(公告)日：2024-10-31

申请号：US18309408

申请日：2023-04-28

申请人： Joon Bu Park

发明人： Joon Bu Park

IPC分类号： H01L23/15 ,  H01L23/14 ,  H01L23/29 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L23/15 ,  H01L23/147 ,  H01L23/291 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06565 ,  H01L2225/06589

摘要： A circuit chip includes a first body having a negative Poisson's ratio; a second body having a positive Poisson's ratio, wherein the first body and the second body are stacked on one another and thermally coupled to one another; and a first integrated circuit embedded in the second body.

公开(公告)号：US20240355712A1

公开(公告)日：2024-10-24

申请号：US18303072

申请日：2023-04-19

申请人： QUALCOMM Incorporated

发明人： Michelle Yejin Kim ,  Hong Bok We ,  Joan Rey Villarba Buot ,  Kuiwon Kang

IPC分类号： H01L23/488 ,  H01L21/48 ,  H01L23/14

CPC分类号： H01L23/488 ,  H01L21/486 ,  H01L23/142 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H10B80/00

摘要： A substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength. In one aspect, a substrate comprises a core layer. The core layer comprises a metal core, the metal core having a first surface and a second surface opposite the first surface. The core layer further comprises a first insulation layer on the first surface and a second insulation layer on the second surface. The substrate further comprises a first metallization structure adjacent to the first insulation layer and a second metallization structure adjacent to the second insulation layer. The metal core provides electrical shielding of signals/power routed through the metal core for noise coupling reduction allowing a higher density of signal and power paths to be supported in substrate, while also strengthening structural integrity to prevent or reduce warpage in the IC package.

公开(公告)号：US12100761B2

公开(公告)日：2024-09-24

申请号：US17578259

申请日：2022-01-18

申请人： Intel Corporation

发明人： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC分类号： H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417 ,  H01L23/15

CPC分类号： H01L29/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L23/145 ,  H01L23/15 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

摘要： An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US20240313043A1

公开(公告)日：2024-09-19

申请号：US18675658

申请日：2024-05-28

申请人： ROHM CO., LTD.

发明人： Bungo TANAKA

IPC分类号： H01L25/16 ,  H01L23/00 ,  H01L23/14 ,  H01L29/92

CPC分类号： H01L28/75 ,  H01L23/147 ,  H01L24/32 ,  H01L24/48 ,  H01L25/162 ,  H01L28/86 ,  H01L29/92 ,  H01L2224/32235 ,  H01L2224/48248

摘要： An insulation chip includes an element insulation layer, a first capacitor, and a second capacitor. The first capacitor includes a first front surface-side electrode plate and a first back surface-side electrode plate that are disposed opposite each other. The second capacitor includes a second front surface-side electrode plate and a second back surface-side electrode plate. The second front surface-side electrode plate and the second back surface-side electrode plate are opposed to each other. In the element insulation layer, the first back surface-side electrode plate and the second back surface-side electrode plate are electrically connected. This signal transmission device includes: a first chip including a first circuit; the insulation chip; and a second chip including a second circuit configured to perform at least one of transmission and reception of a signal with the first circuit via the insulation chip.

公开(公告)号：US20240312795A1

公开(公告)日：2024-09-19

申请号：US18604588

申请日：2024-03-14

申请人： Infineon Technologies Austria AG

发明人： Alexander Roth

IPC分类号： H01L21/48 ,  H01L23/14 ,  H01L23/498

CPC分类号： H01L21/4846 ,  H01L23/498 ,  H01L23/142 ,  H01L23/49894

摘要： A semiconductor module includes a first metal layer, a ceramic layer applied on the first metal layer, a second metal layer applied at least in part on the ceramic layer, and a semiconductor die attached on a portion of the second metal layer. A method for fabricating the semiconductor module is also described.

公开(公告)号：US20240304538A1

公开(公告)日：2024-09-12

申请号：US18591580

申请日：2024-02-29

申请人： Infineon Technologies AG

发明人： Christoph Bayer ,  Matthias Bürger ,  Ulrich Nolten ,  Mark Essert

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L25/00 ,  H01L25/07

CPC分类号： H01L23/49844 ,  H01L23/14 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/181

摘要： A power semiconductor module arrangement includes: a substrate having a dielectric insulation layer and a first metallization layer arranged on a first surface of the dielectric insulation layer; at least one semiconductor body arranged on and attached to the first metallization layer by an electrically conductive connection layer; and at least one electrically conducting element arranged on the first metallization layer. The first metallization layer is a structured layer having a plurality of different sub-sections. The first metallization layer has a uniform thickness in a vertical direction, the vertical direction being perpendicular to the first surface of the dielectric insulation layer. Each electrically conducting element is arranged on and covers a subarea of a sub-section, thereby increasing a cross-sectional area of the subarea of the respective sub-section. Each electrically conducting element includes an electrically conductive connection layer without a semiconductor body arranged thereon.

公开(公告)号：US12068270B2

公开(公告)日：2024-08-20

申请号：US17112567

申请日：2020-12-04

申请人： Samsung Electronics Co., Ltd.

发明人： Jongyoun Kim

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/14 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

摘要： A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.

公开(公告)号：US20240266189A1

公开(公告)日：2024-08-08

申请号：US18635567

申请日：2024-04-15

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Sung Geun Kang ,  Yong Song ,  Wang Gu Lee ,  Eun Young Lee ,  Seo Yeon Ahn ,  Pil Je Sung

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L23/00 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2021/60022 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105

摘要： A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

公开(公告)号：US20240250012A1

公开(公告)日：2024-07-25

申请号：US18402698

申请日：2024-01-02

申请人： Chung W. Ho

发明人： Chung W. Ho

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/49838 ,  H01L23/14 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1815

摘要： A package carrier includes a redistribution circuit layer, a plurality of first conductive pillars, and a package mold plate. The redistribution circuit layer has a first surface and a second surface opposite to each other, and includes a plurality of redistribution circuits, a plurality of conductive vias, a plurality of dielectric layers, and a plurality of output pads. The conductive vias are flush with the first surface, and the output pads protrude from the second surface. The first conductive pillars are disposed within the package mold plate, and are adjacent to the first surface of the redistribution circuit layer and also electrically connected to part of the conductive vias. The package mold plate is adjacent to the first surface of the redistribution circuit layer and has a recess in a middle region of the package mold plate. The recess exposes the first conductive pillars. A thickness of an edge region of the package mold plate provides mechanical stability, so that the redistribution circuit layer attached to it on all four sides will not be deformed.