公开(公告)号：US20250046681A1

公开(公告)日：2025-02-06

申请号：US18924132

申请日：2024-10-23

Applicant: DAI NIPPON PRINTING CO., LTD.

Inventor： Satoru KURAMOCHI

IPC: H01L23/48 ,  B23K26/382 ,  C03C15/00 ,  C03C17/36 ,  C03C17/40 ,  C03C23/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/15 ,  H01L23/32 ,  H01L23/498 ,  H01L23/532

Abstract: A through electrode substrate includes a substrate having a through hole extending through between a first face and a second face, a diameter of the through hole not having a minimum value inside the through hole; and a conductor arranged inside the through hole, wherein the through hole has a shape having a value obtained by summing a first to an eighth inclination angle at a first to an eighth position, respectively, of an inner face of the through hole of 8.0° or more, each of the first to the eighth inclination angle is an angle of the inner face with respect to a center axis of the through hole, and the first to the eighth position correspond to positions at distances of 6.25%, 18.75%, 31.25%, 43.75%, 56.25%, 68.75%, 81.25%, and 93.75%, respectively, from the first face in a section from the first face to the second face.

公开(公告)号：US12219737B2

公开(公告)日：2025-02-04

申请号：US16445470

申请日：2019-06-19

Applicant: International Business Machines Corporation

Inventor： Oblesh Jinka ,  Salvatore Bernardo Olivadese ,  Sean Hart ,  Nicholas Torleiv Bronn ,  Jerry M. Chow ,  Markus Brink ,  Patryk Gumann ,  Daniela Florentina Bogorin

IPC: H05K7/20 ,  G06F30/20 ,  G06N10/00 ,  H01L21/265 ,  H01L23/31 ,  H01L23/32 ,  H01L31/02 ,  F28D21/00 ,  G06F113/20

Abstract: A thermalization structure is formed using a cover configured with a set of pillars, the cover being a part of a cryogenic enclosure of a low temperature device (LTD). A chip including the LTD is configured with a set of cavities, a cavity in the set of cavities having a cavity profile. A pillar from the set of pillars and corresponding to the cavity has a pillar profile such that the pillar profile causes the pillar to couple with the cavity of the cavity profile within a gap tolerance to thermally couple the chip to the cover for heat dissipation in a cryogenic operation of the chip.

公开(公告)号：US20250022813A1

公开(公告)日：2025-01-16

申请号：US18902442

申请日：2024-09-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/32 ,  H01L25/065

Abstract: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

公开(公告)号：US20240282684A1

公开(公告)日：2024-08-22

申请号：US18641480

申请日：2024-04-22

Applicant: RESONAC CORPORATION

Inventor： Kazuyuki MITSUKURA ,  Masaya TOBA ,  Yoshinori EJIRI ,  Kazuhiko KURAFUCHI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/12 ,  H01L23/14 ,  H01L23/32 ,  H01L23/538 ,  H01L25/065 ,  H05K1/09

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/12 ,  H01L23/145 ,  H01L23/32 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L2225/06506 ,  H01L2225/06548 ,  H01L2225/06572 ,  H05K1/09

Abstract: An organic interposer includes: a first organic insulating layer including a groove; a first metal wire located in the groove; a barrier metal material covering the first metal wire; and a second metal wire located above the first metal wire, wherein the barrier metal material includes: a first barrier metal film interposed between the first metal wire and an inner surface of the groove; and a second barrier metal film located on the first metal wire, and wherein the second metal wire is in contact with both of the first barrier metal film and the second barrier metal film.

公开(公告)号：US11959939B2

公开(公告)日：2024-04-16

申请号：US17468014

申请日：2021-09-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shih-Ting Lin

IPC: G01R1/04 ,  G01R31/28 ,  G11C29/56 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01R12/70

CPC classification number: G01R1/0466 ,  G01R31/2886 ,  G11C29/56 ,  H01L23/32 ,  H01L23/49827 ,  H01L24/67 ,  H01R12/7076 ,  H01L24/14 ,  H01L2224/1412 ,  H01L2224/67 ,  H01L2924/1436 ,  H01R2201/20

Abstract: The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.

公开(公告)号：US20240079343A1

公开(公告)日：2024-03-07

申请号：US18507176

申请日：2023-11-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY

IPC: H01L23/544 ,  H01L23/14 ,  H01L23/32 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/145 ,  H01L23/32 ,  H01L25/0655

Abstract: Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.

公开(公告)号：US11769718B2

公开(公告)日：2023-09-26

申请号：US17815421

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/498 ,  G01R1/04 ,  H01L21/48 ,  H01L21/683 ,  H01L23/32 ,  H01L23/00 ,  H01L25/065 ,  H05K1/14 ,  H05K3/46 ,  H05K7/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49811 ,  G01R1/0433 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H05K1/141 ,  H05K3/4682 ,  H05K7/1053 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4694

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

公开(公告)号：US20230299033A1

公开(公告)日：2023-09-21

申请号：US18324514

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuan-Yu Huang ,  Li-Chung Kuo ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Tsung-Yu Chen ,  Chien-Yuan Huang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/32

CPC classification number: H01L24/27 ,  H01L24/94 ,  H01L25/0657 ,  H01L23/32 ,  H01L24/95 ,  H01L2021/60097

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

公开(公告)号：US11764168B2

公开(公告)日：2023-09-19

申请号：US17313229

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hui-Ting Lin ,  Chin-Fu Kao ,  Chen-Shien Chen

IPC: H01L21/50 ,  H01L23/32 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/50 ,  H01L23/32

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate having a surface. The chip package structure includes a chip structure over the surface of the wiring substrate. The chip package structure includes an antiwarpage structure over the surface of the wiring substrate. The antiwarpage structure surrounds the chip structure. The chip package structure includes a first anchor structure affixed to the surface of the wiring substrate and adjacent to a first lower portion of the antiwarpage structure. The first lower portion is between the first anchor structure and the chip structure, and the first anchor structure is electrically isolated from the chip structure.

公开(公告)号：US11652015B2

公开(公告)日：2023-05-16

申请号：US17182571

申请日：2021-02-23

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Yong Ai Ong ,  Chuyao Tai

IPC: H01L23/32 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/32 ,  H01L23/367 ,  H01L23/562

Abstract: Provided herein are semiconductor packages with improved clamps. In some embodiments, a semiconductor package may include a housing having a wall extending from a main body, and a set of support walls extending from the wall. The semiconductor package may further include a clamp extending between the set of support walls, the clamp having a first planar section coupled to a first support wall of the set of support walls, a second planar section coupled to a second support wall of the set of support walls, and a third planar section between the first and second planar sections. The third planar section may include an opening operable to receive a fastener, and a plurality of stress relief openings.