公开(公告)号：US12040246B2

公开(公告)日：2024-07-16

申请号：US17033080

申请日：2020-09-25

申请人： Intel Corporation

发明人： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488 ,  H01L21/60

CPC分类号： H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

摘要： An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US12021038B2

公开(公告)日：2024-06-25

申请号：US17345086

申请日：2021-06-11

申请人： MACOM Technology Solutions Holdings, Inc.

发明人： Margaret Barter ,  Timothy Boles

IPC分类号： H01L23/544 ,  H01L21/48 ,  H01L21/67 ,  H01L23/488

CPC分类号： H01L23/544 ,  H01L21/4814 ,  H01L21/67282 ,  H01L23/488 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433

摘要： A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.

公开(公告)号：US11901320B2

公开(公告)日：2024-02-13

申请号：US18064371

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC分类号： H01L21/76 ,  H01L21/56 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/683 ,  H01L25/10

CPC分类号： H01L24/06 ,  H01L21/565 ,  H01L21/76885 ,  H01L23/3185 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06179 ,  H01L2224/06515 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81805 ,  H01L2224/83005 ,  H01L2224/838 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/19 ,  H01L2224/83005 ,  H01L2224/18 ,  H01L2924/0001

摘要： A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

公开(公告)号：US20230411581A1

公开(公告)日：2023-12-21

申请号：US18459763

申请日：2023-09-01

申请人： ROHM CO., LTD.

发明人： Masahiko KOBAYAKAWA ,  Kazuhiro MIREBA ,  Shintaro YASUDA ,  Junichi ITAI ,  Taisuke OKADA

IPC分类号： H01L33/62 ,  H01L23/495 ,  H01L23/31 ,  H01L23/488 ,  H01L33/48 ,  H01L33/52 ,  H01L25/075 ,  H01L33/64 ,  H01L33/54 ,  H01L23/48 ,  H01L33/50 ,  H01L33/56 ,  H01L33/60

CPC分类号： H01L33/62 ,  H01L23/49541 ,  H01L23/4951 ,  H01L23/31 ,  H01L23/488 ,  H01L33/48 ,  H01L23/49575 ,  H01L23/49517 ,  H01L33/52 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/642 ,  H01L33/64 ,  H01L23/49568 ,  H01L33/483 ,  H01L33/54 ,  H01L23/48 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49548 ,  H01L33/502 ,  H01L33/56 ,  H01L33/60 ,  H01L33/647 ,  H01L25/167

摘要： A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.

公开(公告)号：US11798932B2

公开(公告)日：2023-10-24

申请号：US17855664

申请日：2022-06-30

申请人： Intel Corporation

发明人： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/02 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/488 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H01L23/00 ,  H05K1/11 ,  H05K3/40 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48472 ,  H01L2224/48227 ,  H01L2924/00

摘要： An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US11791228B2

公开(公告)日：2023-10-17

申请号：US16380486

申请日：2019-04-10

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Kristof Darmawikarta ,  Roy Dittler ,  Jeremy Ecton ,  Darko Grujicic

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/488

CPC分类号： H01L23/3114 ,  H01L23/3128 ,  H01L23/488

摘要： Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

公开(公告)号：US11729915B1

公开(公告)日：2023-08-15

申请号：US17700657

申请日：2022-03-22

申请人： TactoTek Oy

发明人： Tomi Simula ,  Tapio Rautio

IPC分类号： H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/22 ,  H05K3/28 ,  H05K3/34 ,  H05K3/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L21/66 ,  H01L21/78 ,  H01L21/673 ,  H01L23/00 ,  H01L23/02 ,  H01L23/04 ,  H01L23/28 ,  H01L23/48 ,  H01L23/49 ,  H01L23/52 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H01L23/552 ,  H05K1/03 ,  H05K1/11 ,  H05K3/12

CPC分类号： H05K3/284 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/0067 ,  H05K3/1283 ,  H05K2203/1316 ,  H05K2203/1322

摘要： The method for manufacturing a number of electrical nodes, wherein the method includes providing a number of electronic circuits onto a first substrate, such as on a printed circuit board or other electronics substrate, optionally, a low-temperature co-fired ceramic substrate, wherein each one of the electronic circuits includes a circuit pattern and at least one electronics component in connection with the circuit pattern, wherein the electronic circuits are spaced from each other on the first substrate, thereby defining a blank area surrounding each one of the number of electronic circuits, respectively, and providing potting or casting material to embed each one of the number of electronic circuits in the potting or casting material, and, subsequently, hardening, optionally including curing, the potting or casting material to form a filler material layer of the number of electrical nodes.

公开(公告)号：US11713241B2

公开(公告)日：2023-08-01

申请号：US17444212

申请日：2021-08-02

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Chih-Ming Chen ,  Yuan-Chih Hsieh ,  Chung-Yi Yu

IPC分类号： B81B7/00 ,  B81C1/00 ,  H01L23/488 ,  H01L25/00 ,  H01L23/00

CPC分类号： B81C1/00269 ,  B81B7/0041 ,  B81C1/00 ,  B81C1/00238 ,  H01L23/488 ,  H01L25/50 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2207/012 ,  B81B2207/093 ,  B81C2201/019 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/035 ,  B81C2203/036 ,  H01L24/02 ,  H01L24/06 ,  H01L24/81

摘要： The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

公开(公告)号：US20230187416A1

公开(公告)日：2023-06-15

申请号：US18165056

申请日：2023-02-06

申请人： ROHM CO., LTD.

发明人： Kenji HAYASHI ,  Masashi HAYASHIGUCHI

IPC分类号： H01L25/07 ,  H01L23/36 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H02M7/48

CPC分类号： H01L25/07 ,  H01L23/36 ,  H01L23/488 ,  H01L24/06 ,  H01L24/49 ,  H01L25/18 ,  H02M7/48 ,  H01L2224/0603 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/13055

摘要： A semiconductor power module including an insulating substrate having one surface and another surface, an output side terminal arranged at a one surface side of the insulating substrate, a first power supply terminal arranged at the one surface side of the insulating substrate, a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, and arranged at an other surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate, a first switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the first power supply terminal, and a second switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the second power supply terminal.

公开(公告)号：US20230154863A1

公开(公告)日：2023-05-18

申请号：US18155672

申请日：2023-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/488 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/31 ,  H01L23/488 ,  H01L23/5384 ,  H01L24/14

摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.