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公开(公告)号:US12131981B2
公开(公告)日:2024-10-29
申请号:US18357931
申请日:2023-07-24
发明人: Yushuang Yao , Vemmond Jeng Hung Ng
IPC分类号: H01L23/492 , H01L21/48
CPC分类号: H01L23/4924 , H01L21/4871
摘要: Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.
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2.
公开(公告)号:US20240321774A1
公开(公告)日:2024-09-26
申请号:US18399519
申请日:2023-12-28
发明人: Kitae Park , Chiwan Song , Seonkyu Kim , Hyunna Bae , Seungmin Baek , Yongjae Song , Joonseok Oh , Jaewook Jung , Seokil Hong
IPC分类号: H01L23/00 , H01L21/02 , H01L21/3205 , H01L23/31 , H01L23/492 , H01L25/065 , H10B80/00
CPC分类号: H01L23/562 , H01L21/0214 , H01L21/02249 , H01L21/02252 , H01L21/32055 , H01L23/3135 , H01L23/4926 , H01L24/48 , H01L25/0657 , H10B80/00 , H01L2224/48149 , H01L2224/48227 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/3511 , H01L2924/3512
摘要: The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.
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公开(公告)号:US12087670B1
公开(公告)日:2024-09-10
申请号:US18446841
申请日:2023-08-09
IPC分类号: H01L23/00 , H01L21/48 , H01L23/492
CPC分类号: H01L23/4922 , H01L21/4803 , H01L21/4878 , H01L23/4924
摘要: In-Substrate Structures (ISS) and isolation regions, including, but not limited to Through Metal Vias (TMV), Dielectric Isolation Vias (DIV), and Dielectric Isolation Pockets (DIP) formed in a metal substrate to provide enhanced operations for semiconductor packages incorporating a metal substrate, and methods of making the same.
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公开(公告)号:US12057375B2
公开(公告)日:2024-08-06
申请号:US18324479
申请日:2023-05-26
申请人: ROHM CO., LTD.
发明人: Maiko Hatano
IPC分类号: H01L23/492 , H01L23/00 , H01L23/31
CPC分类号: H01L23/4924 , H01L23/3114 , H01L24/83 , H01L2224/8384
摘要: A semiconductor device A1 includes a semiconductor element 10A having an element obverse face 101 and an element reverse face 102, the element obverse face 101 having an obverse face electrode 11 formed thereon and the element reverse face 102 having a reverse face electrode 12 formed thereon, a conductive substrate 22A including an obverse face 221A opposed to the element reverse face 102, and to which the reverse face electrode 12 is conductively bonded, a conductive substrate 22B including an obverse face 221B and spaced from the conductive substrate 22A in a width direction x, and a lead member 51 extending in the width direction x, and electrically connecting the obverse face electrode 11 and the conductive substrate 22B. The lead member 51 is located ahead of the obverse face 221B in the direction in which the obverse face 221B is oriented, and bonded to the obverse face electrode 11 via a lead bonding layer 32. The conductive substrate 22A, the semiconductor element 10A, and the lead bonding layer 32 overlap with the conductive substrate 22B, as viewed in the width direction x.
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公开(公告)号:US20240178100A1
公开(公告)日:2024-05-30
申请号:US18464511
申请日:2023-09-11
发明人: Naoki YOSHIMATSU , Shintaro ARAKI
IPC分类号: H01L23/373 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/492 , H01L23/495
CPC分类号: H01L23/3736 , H01L21/565 , H01L23/3107 , H01L23/4924 , H01L23/4952 , H01L23/49562 , H01L23/49579 , H01L24/45 , H01L2224/45124 , H01L2924/13055
摘要: The semiconductor device includes: a heat spreader; a first solder layer; a second solder layer; a semiconductor element including a first surface bonded to the heat spreader through the first solder layer, a second surface facing the first surface, a first electrode disposed on the first surface, and a second electrode disposed on the second surface; a block bonded to the second electrode through the second solder layer; a sheet including a first portion, and a second portion having insulating properties and being in contact with the heat spreader; a first lead frame welded to the heat spreader; a second lead frame welded to the block; and a sealant having insulating properties and sealing the first and second lead frames, the heat spreader, the first and second solder layers, the semiconductor element, and the block.
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公开(公告)号:US11990391B2
公开(公告)日:2024-05-21
申请号:US17475102
申请日:2021-09-14
申请人: DENSO CORPORATION
IPC分类号: H01L23/492 , H01L23/31 , H01L23/367 , H01L25/07
CPC分类号: H01L23/492 , H01L23/3107 , H01L23/367 , H01L25/072
摘要: In a semiconductor device, a first metal plate faces a first semiconductor element and a second semiconductor element and is electrically connected to a second terminal. A second metal plate faces the first metal plate while interposing the first semiconductor element between the first and second metal plates, and is electrically connected to a first terminal. A third metal plate faces the first metal plate while interposing the second semiconductor element between the first and third metal plates. The first semiconductor element has an electrode on a surface adjacent to the second metal plate and electrically connected to the second metal plate, and an electrode on a surface adjacent to the first metal plate and electrically connected to the third metal plate. The first semiconductor element is thermally connected to the first metal plate while being electrically insulated from the first metal plate by an insulator.
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7.
公开(公告)号:US20240136782A1
公开(公告)日:2024-04-25
申请号:US18494952
申请日:2023-10-25
发明人: Henry Todd Young , Alvaro Jorge Mari Curbelo , Jason Daniel Kuttenkuler , Tiziana Bertoncelli , Sean Patrick Cillessen
CPC分类号: H01R25/162 , H01L23/46 , H01L23/492 , H01L25/115 , H01R43/16 , H02G5/005 , H02M7/003 , H05K7/2089 , H05K7/20927 , H02M7/537
摘要: A bus bar includes a load terminal connector comprising a conductive plate that extends from a first edge to an opposite second edge and extends from a third edge to an opposite fourth edge. The third and fourth edges extend from the first edge to the second edge. The plate includes a window opening located between the first and second edges and between the third and fourth edges. The plate also includes a slot extending into the plate from the first edge to the window opening. The plate includes first and second sets of openings configured to receive connections with first and second power terminals of switch packages. The first set of openings and the second set of openings are located on opposite sides of the slot.
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公开(公告)号:US11942335B2
公开(公告)日:2024-03-26
申请号:US17989196
申请日:2022-11-17
发明人: Achim Muecke , Arthur Unrau
IPC分类号: H01L21/48 , H01L23/492 , H01L25/00 , H01L25/07 , H01L25/18
CPC分类号: H01L21/4871 , H01L23/4922 , H01L25/50 , H01L25/072 , H01L25/18
摘要: A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.
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公开(公告)号:US11908834B2
公开(公告)日:2024-02-20
申请号:US17741402
申请日:2022-05-10
发明人: Vivek Arora , Woochan Kim
IPC分类号: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/492 , H01L23/495 , H01L21/56 , H01F27/40 , H01F27/06 , H01L25/00
CPC分类号: H01L25/0655 , H01F27/06 , H01F27/40 , H01L21/56 , H01L23/3107 , H01L23/4924 , H01L23/49503 , H01L23/49575 , H01L24/48 , H01L24/92 , H01L25/50 , H01L2224/48195 , H01L2224/92247
摘要: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.
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公开(公告)号:US11908761B2
公开(公告)日:2024-02-20
申请号:US18099347
申请日:2023-01-20
发明人: Seung Nam Son , Dong Hyun Khim , Jin Kun Yoo
IPC分类号: H01L23/31 , H01L23/492 , H01L23/373 , H01L23/40
CPC分类号: H01L23/31 , H01L23/3735 , H01L23/4926 , H01L2023/4087
摘要: In one example, an electronic device comprises a base substrate comprising a base substrate conductive structure, a first electronic component over a first side of the base substrate, an encapsulant over the first side of the base substrate, wherein the encapsulant contacts a lateral side of the electronic component, an interposer substrate over a first side of the encapsulant and comprising an interposer substrate conductive structure, and a vertical interconnect in the encapsulant and coupled with the base substrate conductive structure and the interposer substrate conductive structure. A first one of the base substrate or the interposer substrate comprises a redistribution layer (RDL) substrate, and a second one of the base substrate or the interposer substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.
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